gem5.git
2019-02-05 Javier Buenocpu: Made the Loop Predictor a SimObject
2019-02-05 Jairo Balartcpu: Made TAGE a SimObject that can be used by other...
2019-02-05 Austin Harrisriscv: Get rid of ISA specific register types in Interr...
2019-02-01 Javier Buenomem-cache: Updated version of the Signature Path Prefetcher
2019-02-01 Anouk Van Laerdev, arm: Removed contextId variable
2019-02-01 Gabe Blackcpu, arch: Replace the CCReg type with RegVal.
2019-01-31 Andreas Sandbergpython: Remove getCode() type workaround
2019-01-31 Andreas Sandbergsim: Prepare C++ side for Python 3
2019-01-31 Andreas Sandbergtests: Add a helper to run external scripts
2019-01-31 Andreas Sandbergtests: Don't override tick rate in Ruby tests
2019-01-31 Gabe Blackpower: Get rid of some ISA specific register types.
2019-01-31 Gabe Blacknull: Get rid of some register type definitions.
2019-01-31 Gabe Blackmips: Stop using architecture specific register types.
2019-01-31 Gabe Blackalpha: Stop using architecture specific register types.
2019-01-31 Gabe Blackx86: Stop using/defining some ISA specific register...
2019-01-31 Gabe Blackriscv: Get rid of some ISA specific register types.
2019-01-31 Gabe Blackarch: cpu: Rename *FloatRegBits* to *FloatReg*.
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers
2019-01-30 Giacomo Travagliniconfigs: Enable DTB autogeneration in starter_fs.py
2019-01-30 Giacomo Travagliniarch-arm, configs: Create single instance of DTB autoge...
2019-01-28 Ciro Santillitests: fix arm regression due to kernel not found
2019-01-25 Ciro Santilliconfigs: fs.py remove --generate-dtb and enable it...
2019-01-25 Ciro Santilliconfigs, arch-arm: don't search for default DTB and...
2019-01-25 Giacomo Travagliniarch-arm: Remove floatReg operand type
2019-01-25 Giacomo Travagliniarch-arm: Use VecElem instead of FloatReg for FP instru...
2019-01-25 Giacomo Travagliniarch: Fix VecElem Operand generation in ISA parser
2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the...
2019-01-25 Giacomo Travaglinicpu: O3 rename using the flatIndex instead of index
2019-01-25 Giacomo Travagliniarch-arm: Inital vector rename mode depending on A32/A64
2019-01-25 Giacomo Travaglinicpu: Fix VecElemClass bugs in cpu models
2019-01-25 Giacomo Travaglinicpu: Add VecElem entries in MinorCPU Scoreboard
2019-01-25 Giacomo Travagliniarch-arm: Remove unused float operands
2019-01-25 Giacomo Travagliniarch: Provide traceback when parsing ISA code
2019-01-25 Nicholas Lindsaypython: Always throw TypeError on slave-slave connections
2019-01-24 Gabe Blackhsail: Remove the MiscReg type.
2019-01-24 Gabe Blackbase: arch: Get rid of the now unused FloatRegVal type.
2019-01-24 Ciro Santillidev-arm: fix --generate-dtb for ARM
2019-01-24 Rekai Gonzalez... cpu-o3: O3 LSQ Generalisation
2019-01-23 Giacomo Travagliniarch-arm: Implement LoadAcquire/StoreRelease in AArch32
2019-01-23 Giacomo Travagliniarch-arm: IsStoreConditional flag set depending on...
2019-01-23 Giacomo Travagliniarch-arm: Remove SWP and SWPB instructions
2019-01-23 Gabe Blacksystemc: Fix TLM related includes.
2019-01-23 Gabe Blackarm: Replace MiscReg with RegVal in utility.(hh|cc).
2019-01-23 Zicong Wangmem-ruby: Fix missing TBE allocation and deallocation
2019-01-22 Gabe Blacksparc: Get rid of some register type definitions.
2019-01-22 Gabe Blackarch: cpu: Stop passing around misc registers by reference.
2019-01-22 Gabe Blackarm: Get rid of some register type definitions.
2019-01-22 Gabe Blackarm: dev: Replace ArmISA::MiscReg with RegVal in the...
2019-01-22 Ciro Santilliarch-arm: implement the GDB XML target description...
2019-01-22 Ciro Santilliext: import GDB XML target description files for arm
2019-01-22 Ciro Santilliscons: add helpers to access GDB XML description files
2019-01-22 Ciro Santilliscons: allow embedding arbitrary blobs into the gem5...
2019-01-22 Ciro Santillibase: add support for GDB's XML architecture definition
2019-01-22 Giacomo Travagliniarch-arm: Move AArch32 IMPLEMENTATION DEFINED registers
2019-01-22 Sascha Bischoffmem: Add tryTiming suppport to CommMonitor
2019-01-22 Brandon Pottersim-se add readv and modifies writev
2019-01-22 Brandon Pottersim-se: add ability to get/set sock metadata
2019-01-22 Brandon Pottersim-se: add syscalls related to polling
2019-01-22 Brandon Pottersim-se: add calls for network transmissions
2019-01-22 Brandon Pottersim-se: add socket-based functionality
2019-01-18 Daniel R. Carvalhobase: Fix unitialized storage
2019-01-17 Gabe Blacktests: Fix tests/main.py so it can be run from anywhere.
2019-01-17 Nikos Nikolerismem: Allow inserts in the begining of a packet queue
2019-01-17 Nikos Nikolerismem: Determine if a packet queue forces ordering at...
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtCommitPolicy a Param.ScopedEnum
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtROBPolicy a Param.ScopedEnum
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtIQPolicy a Param.ScopedEnum
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtLSQPolicy a Param.ScopedEnum
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtFetchPolicy a Param.ScopedEnum
2019-01-17 Nikos Nikolerispython: Add support for scoped enums
2019-01-16 Gabe Blackcpu: dev: sim: gpu-compute: Banish some ISA specific...
2019-01-16 Gabe Blackarch: Make the ISA register types aliases for the globa...
2019-01-16 Gabe Blackarm: Make the fp register types 64 bits.
2019-01-16 Javier Buenomem-cache: Access Map Pattern Matching Prefetcher
2019-01-16 Javier Buenomem-cache: Signature Path Prefetcher
2019-01-16 Javier Buenomem-cache: allow prefetchers to emit page crossing...
2019-01-16 Javier Buenomem-cache: virtual address support for prefetchers
2019-01-16 Giacomo Travagliniarch-arm: Read VMPIDR instead of MPIDR when EL2 is...
2019-01-16 Anouk Van Laerarch-arm: Added TLBI_ALL EL2 instruction
2019-01-16 Alec Roelkearch-riscv: Add interrupt handling
2019-01-16 Alec Roelkearch-riscv: Fix reset function and style
2019-01-15 Giacomo Travaglinicpu: Fix usage of setArchVecElem
2019-01-15 Giacomo Travagliniarch-arm: Fix usage of RegId constructor for VecElem
2019-01-14 Gabe Blackarm: Stop using the FloatReg and FloatRegBits types.
2019-01-14 Gabe Blackconfig: De-nest the code in Port.splice().
2019-01-14 Gabe Blackconfig: Fix an error message in Port.splice().
2019-01-11 Andrea Mondelliscons: added support of default Python installation...
2019-01-11 Andrea Mondellimisc: updated shabang for python script
2019-01-10 Javier Setoainsim-se, arch-arm: Add support for getdents64
2019-01-10 Andreas Sandbergarch-arm, sim-se: Add support for TLS in clone
2019-01-10 Andreas Sandbergarch-arm, sim-se: Fix incorrect SP handling in clone
2019-01-10 Andreas Sandbergsim-se: Refactor clone to avoid most ifdefs
2019-01-10 Andreas Sandbergsim-se: Correctly calculate next PC in clone
2019-01-10 Andreas Sandbergsim-se: Use CONFIG_CLONE_BACKWARDS for Arm
2019-01-10 Javier Setoainarch-arm, sim-se: Wire up syscalls needed for pthreads
2019-01-10 Jairo Balartdev-arm: Add a VExpress_GEM5_V2 platform with GICv3...
2019-01-10 Jairo Balartdev-arm: Add a GICv3 model
2019-01-10 Giacomo Travaglinibase: Make it possible to convert strings to enums
2019-01-10 Gabe Blacksystemc: Fix a function which was broken during style...
2019-01-09 Ivan Pizarroarch-arm: Additional bits in misc ARM registers to...
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