2021-12-31 |
Robin Ole Heinemann | hdl.ast: fix typo |
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2021-12-31 |
whitequark | Update .gitignore. |
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2021-12-31 |
whitequark | vendor.intel: don't use `write_verilog -decimal`. |
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2021-12-31 |
whitequark | vendor.intel: double-quote Tcl values rather than brace... |
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2021-12-31 |
whitequark | vendor.xilinx_{7series,ultrascale}: don't use `write_ve... |
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2021-12-31 |
whitequark | build.plat: skip clock constraints on unused signals. |
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2021-12-31 |
whitequark | vendor.xilinx_{7series,ultrascale}: add (*keep*) on... |
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2021-12-31 |
whitequark | hdl.ast: add const-shift operations. |
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2021-12-31 |
whitequark | hdl.ast: clarify docs for Value.rotate_{left,right}. |
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2021-12-31 |
whitequark | hdl.dsl: check for unique domain name. |
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2021-12-31 |
whitequark | back.rtlil: handle signed and large Instance parameters... |
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2021-12-31 |
whitequark | tracer: fix get_var_name() to work on toplevel attributes. |
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2021-12-31 |
Gwenhael Goavec... | vendor.lattice_machxo2: generate binary bitstreams. |
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2021-12-31 |
whitequark | plat, vendor: systematically escape net and file names... |
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2021-12-31 |
whitequark | back.rtlil: fix incorrect escaping of signed parameters. |
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2021-12-31 |
whitequark | hdl.ast: use SignalSet, not ValueSet, for _[lr]hs_signa... |
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2021-12-31 |
awygle | lib.fifo: add r_rst output for AsyncFIFO{,Buffered}. |
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2021-12-31 |
awygle | hdl.ir: typecheck `convert(ports=)` more carefully. |
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2021-12-31 |
whitequark | README: link directly to Yosys build instructions. |
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2021-12-31 |
Teguh Hofstee | back.verilog: add workaround for evaluation Verific... |
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2021-12-31 |
Teguh Hofstee | back.verilog: make Yosys version check compatible with... |
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2021-12-31 |
Kate Temkin | vendor: use nextpnr -12k for -12F devices; remove theor... |
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2021-12-31 |
anuejn | hdl.rec: make Record inherit from UserValue. |
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2021-12-31 |
whitequark | back.rtlil: translate enum decoders to Yosys enum attri... |
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2021-12-31 |
whitequark | buil.plat: enable strict undefined behavior in Jinja2. |
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2021-12-31 |
whitequark | back.rtlil: don't emit connections to zero width ports. |
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2021-12-31 |
whitequark | back.rtlil: refuse to create extremely large wires. |
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2021-12-31 |
whitequark | back.rtlil: fix expansion of Part() for partial dummy... |
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2021-12-31 |
whitequark | back.rtlil: fix legalization of Part() with stride. |
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2021-12-31 |
whitequark | Clarify a few comments. NFC. |
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2021-12-31 |
Dan Ravensloft | hdl.ast: add Value.{rotate_left,rotate_right}. |
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2021-12-31 |
whitequark | Travis: require tests to pass on pypy3. |
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2021-12-31 |
whitequark | Travis: upgrade to bionic. |
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2021-12-31 |
whitequark | build.run: fix BuildProducts.extract to work with subdi... |
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2021-12-31 |
whitequark | hdl.rec: improve repr() for Layout. |
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2021-12-31 |
whitequark | hdl.ast: improve repr() for Shape. |
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2021-12-31 |
whitequark | build.plat: don't check for toolchain presence if do_bu... |
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2021-12-31 |
Stuart Olsen | back.pysim: Clear pending updates after they are effected |
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2021-12-31 |
Stuart Olsen | back.pysim: Eliminate duplicate dict lookup in VCD... |
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2021-12-31 |
Stuart Olsen | back.pysim: Reuse clock simulation commands |
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2021-12-31 |
whitequark | hdl.mem: fix source location of ReadPort.en. |
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2021-12-31 |
whitequark | back.pysim: fix emission of undriven traces to VCD... |
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2021-12-31 |
whitequark | setup: bump pyvcd to ~=0.2. |
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2021-12-31 |
Jacob Lifshay | Add support for using non-compat Elaboratable instances... |
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2021-12-31 |
whitequark | setup: tighten version constraint on Jinja2. |
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2021-12-31 |
whitequark | hdl.ast: implement abs() on values. |
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2021-12-31 |
WRansohoff | vendor.lattice_ice40: add support for SB_[LH]FOSC as... |
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2021-12-31 |
Nicolas Robin | vendor: fix typo `async_ff_sync` |
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2021-12-31 |
Stuart Olsen | back.pysim: implement modulus operator. |
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2021-12-31 |
awygle | Correctly handle resets in AsyncFIFO. |
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2020-03-12 |
whitequark | vendor: fix a few issues in commit 2f8669ca. |
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2020-03-08 |
awygle | lib.cdc: extract AsyncFFSynchronizer. |
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2020-02-19 |
whitequark | hdl.ast: fix off-by-1 in Initial.__init__(). |
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2020-02-19 |
whitequark | back.pysim: fix RHS codegen for Cat() and Repl(...... |
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2020-02-19 |
whitequark | back.pysim: optionally allow introspecting generated... |
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2020-02-16 |
awygle | nmigen.compat.genlib.cdc: add PulseSynchronizer. |
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2020-02-16 |
awygle | nmigen.lib.cdc: port PulseSynchronizer. |
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2020-02-14 |
whitequark | Travis: prune dependencies. |
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2020-02-14 |
whitequark | Travis: test on Python 3.8. |
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2020-02-12 |
whitequark | cli: update use of deprecated code. |
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2020-02-12 |
whitequark | back.pysim: accept write_vcd(vcd_file=None). |
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2020-02-09 |
whitequark | setup: update project URLs. |
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2020-02-09 |
whitequark | doc: remove outdated files and references to them. |
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2020-02-08 |
whitequark | README: link to IRC channel. |
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2020-02-08 |
whitequark | README: consolidate requirements in the Installation... |
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2020-02-07 |
whitequark | test_build_res: fix after commit 3e2ecdf2. |
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2020-02-06 |
whitequark | build.res,vendor: place clock constraint on port, not... |
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2020-02-06 |
whitequark | xilinx_{7series,ultrascale}: run `report_methodology`. |
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2020-02-06 |
whitequark | hdl.ast: add Value.{as_signed,as_unsigned}. |
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2020-02-06 |
whitequark | test_lib_fifo: define all referenced FSM states. |
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2020-02-06 |
whitequark | hdl.dsl: make referencing undefined FSM states an error. |
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2020-02-06 |
whitequark | hdl.ir: type check ports. |
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2020-02-06 |
whitequark | back.pysim: emit toplevel inputs in VCD files as well. |
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2020-02-06 |
whitequark | back.pysim: make `write_vcd(traces=)` actually use... |
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2020-02-06 |
whitequark | hdl.dsl: reject name mismatch in `m.domains.<name>... |
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2020-02-06 |
whitequark | hdl.dsl: type check when adding to m.domains. |
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2020-02-06 |
whitequark | hdl.mem: add synthesis attribute support. |
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2020-02-06 |
whitequark | hdl.mem: document Memory. |
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2020-02-04 |
whitequark | hdl.{ast,dsl}: allow whitespace in bit patterns. |
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2020-02-01 |
whitequark | hdl.ast: update documentation for Signal. |
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2020-02-01 |
whitequark | hdl.ast: prohibit shifts by signed value. |
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2020-02-01 |
whitequark | build.plat: align pipeline with Fragment.prepare(). |
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2020-02-01 |
whitequark | hdl.dsl: don't allow inheriting from Module. |
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2020-02-01 |
whitequark | hdl.ast: warn on unused property statements (Assert... |
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2020-02-01 |
whitequark | _unused: extract must-use logic from hdl.ir. |
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2020-01-31 |
whitequark | hdl.dsl: add missing case width check for Enum values. |
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2020-01-31 |
whitequark | README: clarify relationship to Migen. |
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2020-01-31 |
whitequark | hdl.dsl: make `if m.{If,Elif,Else}(...)` a syntax error. |
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2020-01-31 |
whitequark | back.rtlil: don't emit wires for empty signals. |
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2020-01-31 |
Mike Walters | vendor.lattice_ecp5: support internal oscillator (OSCG). |
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2020-01-31 |
Jaro Habiger | build.dsl: allow strings to be used as connector numbers. |
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2020-01-31 |
Sylvain Munaut | vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files... |
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2020-01-27 |
whitequark | Update README. |
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2020-01-18 |
whitequark | hdl.ir: resolve hierarchy conflicts before creating... |
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2020-01-17 |
whitequark | hdl.xfrm: transform drivers as well in DomainRenamer. |
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2020-01-12 |
whitequark | Remove everything deprecated in nmigen 0.1. |
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2020-01-11 |
Staf Verhaegen | Signal: allow to use integral Enum for reset value. |
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2020-01-09 |
schwigi | vendor.intel: fix output enable width for XDR=0 case. |
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2020-01-07 |
Alain Péteut | build.run: fix indentation. |
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2020-01-01 |
whitequark | back.rtlil: do not consider unreachable array elements... |
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