yosys.git
2014-07-20 Clifford WolfAdded support for resource sharing in mux control logic
2014-07-20 Clifford WolfAdded "select -assert-count"
2014-07-20 Clifford WolfSupercell creation for $div/$mod worked all along,...
2014-07-20 Clifford WolfImproved tests/share/generate.py
2014-07-20 Clifford WolfFixed creation of shift supercells in "share" pass
2014-07-20 Clifford WolfSmall fix in tests/vloghtb/run-test.sh
2014-07-20 Clifford WolfActivated tests/share in "make test"
2014-07-20 Clifford WolfAdded "miter -equiv -flatten"
2014-07-20 Clifford WolfAdded call_on_selection() and call_on_module() API
2014-07-20 Clifford WolfAdded tests/vloghtb/test_share.sh
2014-07-20 Clifford WolfAdded tests/share for testing "share" supercell creation
2014-07-20 Clifford WolfAdded "share" supercell creation
2014-07-20 Clifford WolfAdded removing of always inactive cells to "share"...
2014-07-20 Clifford WolfProgress in "share" pass
2014-07-20 Clifford WolfAdded std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
2014-07-20 Clifford WolfAdded SIZE() macro
2014-07-20 Clifford WolfAdded log_cell()
2014-07-20 Clifford WolfProgress in "share" pass
2014-07-20 Clifford WolfAdded tests/vloghtb
2014-07-20 Clifford WolfUse functions instead of always blocks for $mux/$pmux...
2014-07-19 Clifford WolfAdded support for $bu0 to verilog backend
2014-07-19 Clifford WolfStarted to implement real resource sharing
2014-07-19 Clifford WolfFixed log_id() memory corruption
2014-07-19 Clifford WolfImproved memory_share log messages
2014-07-19 Clifford WolfMore verbose memory_share help message
2014-07-19 Clifford WolfAdded SAT-based write-port sharing to memory_share
2014-07-19 Clifford WolfAdded ModWalker helper class
2014-07-19 Clifford WolfSome "const" cleanups in SigMap
2014-07-19 Clifford WolfFixed bug in memory_share feedback-to-en code
2014-07-18 Clifford WolfAdded translation from read-feedback to en-signals...
2014-07-18 Clifford WolfImproved seeding of color rng in show command
2014-07-18 Clifford WolfOnly create collision detect logic in memory_share...
2014-07-18 Clifford WolfBugfix in tests/memories/run-test.sh
2014-07-18 Clifford Wolfadded tests/memories
2014-07-18 Clifford WolfAdded memory_share
2014-07-18 Clifford WolfAdded automatic conversion from RTLIL::SigSpec to std...
2014-07-18 Clifford WolfApply opt_reduce WR_EN opts to the whole mux tree drivi...
2014-07-18 Clifford WolfAdded function-like cell creation helpers
2014-07-18 Clifford WolfAdded log_id() helper function
2014-07-17 Clifford WolfAlso simulate unmapped memories in "make test"
2014-07-17 Clifford WolfImplemented dynamic bit-/part-select for memory writes
2014-07-17 Clifford WolfFixed simlib.v model for $mem
2014-07-17 Clifford WolfAdded support for bit/part select to mem2reg rewriter
2014-07-17 Clifford WolfAdded support for constant bit- or part-select for...
2014-07-17 Clifford WolfImproved opt_reduce handling of mem wr_en mux bits
2014-07-17 Clifford WolfFixed RTLIL::SigSpec::append_bit() for appending constants
2014-07-17 Clifford WolfAdded support for "blackbox" attribute to iopadmap
2014-07-17 Clifford WolfAdded support for "blackbox" attribute to flatten/techmap
2014-07-16 Clifford WolfAdded "inout" ports support to read_liberty
2014-07-16 Clifford WolfSet blackbox attribute in "read_liberty -lib"
2014-07-16 Clifford WolfFixed spelling of "direction" in read_liberty messages
2014-07-16 Clifford WolfMerged new $mem/$memwr WR_EN interface
2014-07-16 Clifford WolfChanged tests/techmap/mem_simple_4x1_map for new $mem...
2014-07-16 Clifford Wolfimproved opt_reduce for $mem/$memwr WR_EN multiplexers
2014-07-16 Clifford Wolfchanges in verilog frontend for new $mem/$memwr WR_EN...
2014-07-16 Clifford WolfChanges to "memory" pass for new $memwr/$mem WR_EN...
2014-07-16 Clifford WolfUpdated simlib to new $mem/$memwr interface
2014-07-16 Clifford WolfChanged the $mem/$memwr WR_EN input to a per-data-bit...
2014-07-16 Clifford WolfAdded note to "make test": use git checkout of iverilog
2014-07-12 Clifford WolfAdded passing of various options to vhdl2verilog
2014-07-11 Clifford WolfUse "verilog -sv" to parse .sv files
2014-07-11 Clifford WolfFixed processing of initial values for block-local...
2014-07-05 Clifford Wolfnow ignore init attributes on non-register wires in...
2014-07-02 Clifford Wolffixed parsing of constant with comment between size...
2014-07-02 Clifford Wolfsmall changes in presentation
2014-06-29 Clifford WolfTiny fix in presentation
2014-06-29 Clifford WolfProgress in presentation
2014-06-28 Clifford WolfAdded links to some liberty files to README
2014-06-26 Clifford WolfProgress in presentation
2014-06-25 Clifford WolfFixed handling of mixed real/int ternary expressions
2014-06-24 Clifford WolfMore found_real-related fixes to AstNode::detectSignWid...
2014-06-22 Clifford WolfProgress in presentation
2014-06-21 Clifford WolfLittle steps in realmath test bench
2014-06-21 Clifford Wolffixed signdness detection for expressions with reals
2014-06-21 Clifford Wolffixed typo
2014-06-21 Clifford WolfProgress in presentation
2014-06-19 Clifford WolfDo not create $dffsr cells with no-op resets in proc_dff
2014-06-17 Clifford WolfAdded test case for AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 Clifford WolfAdded AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 Clifford WolfImproved handling of relational op of real values
2014-06-16 Clifford WolfLittle steps in realmath test bench
2014-06-16 Clifford WolfImproved ternary support for real values
2014-06-16 Clifford WolfUse undef (x/z vs. NaN) rules for real values from...
2014-06-16 Clifford WolfFixed parsing of TOK_INTEGER (implies TOK_SIGNED)
2014-06-16 Clifford WolfAdded found_real feature to AstNode::detectSignWidth
2014-06-15 Clifford WolfAdded more calls to "hierarchy" to README file
2014-06-15 Clifford WolfRemoved long running tests from tests/simple/realexpr...
2014-06-15 Clifford WolfAdded tests/realmath to "make test"
2014-06-15 Clifford WolfImproved AstNode::realAsConst for large numbers
2014-06-15 Clifford WolfImproved realmath test bench
2014-06-15 Clifford WolfImproved parsing of large integer constants
2014-06-15 Clifford WolfImproved AstNode::asReal for large integers
2014-06-14 Clifford Wolfimproved realmath test bench
2014-06-14 Clifford Wolfimproved (fixed) conversion of real values to bit vectors
2014-06-14 Clifford Wolfprogress in realmath test bench
2014-06-14 Clifford WolfFixed relational operators for const real expressions
2014-06-14 Clifford Wolfadded first draft of real math testcase generator
2014-06-14 Clifford WolfProgress in presentation
2014-06-14 Clifford WolfAdded %D and %c select commands
2014-06-14 Clifford WolfAdded support for math functions
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