yosys.git
2020-01-02 Eddie Hungwrite_xaiger: get rid of external_bits dict
2020-01-02 Eddie HungCombine tests to check multiple clock domains
2020-01-02 Eddie Hungsynth_xilinx -dff to work with abc too
2020-01-02 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 Eddie HungAdd 'abc9 -dff' to CHANGELOG
2020-01-02 Eddie HungUpdate doc
2020-01-02 Eddie HungUpdate comments
2020-01-02 Eddie Hungabc9 -keepff -> -dff; refactor dff operations
2020-01-02 Clifford WolfMerge pull request #1609 from YosysHQ/clifford/fix1596
2020-01-02 Clifford WolfAlways create $shl, $shr, $sshl, $sshr cells with unsig...
2020-01-02 Eddie HungMerge pull request #1601 from YosysHQ/eddie/synth_retime
2020-01-02 Eddie HungMerge pull request #1608 from YosysHQ/eddie/ifndef_YOSYS
2020-01-02 Eddie Hungifdef __ICARUS__ -> ifndef YOSYS
2020-01-01 Eddie HungMerge pull request #1606 from YosysHQ/eddie/improve_tests
2020-01-01 Eddie HungRevert insertion of 'reg', leave note behind
2020-01-01 Miodrag MilanovićMerge pull request #1605 from YosysHQ/iopad_fix
2020-01-01 Eddie HungFix anlogic async flop mapping
2020-01-01 Eddie HungClamp -46ps for FDPE* too
2020-01-01 Eddie HungGet rid of (* abc9_keep *) in write_xaiger too
2020-01-01 Eddie HungCleanup abc9, update doc for -keepff option
2020-01-01 Eddie HungRestore abc9 -keepff
2020-01-01 Eddie Hungattributes.count() -> get_bool_attribute()
2020-01-01 Miodrag MilanovicAdded a test case
2020-01-01 Miodrag Milanovictake skip wire bits into account
2020-01-01 Eddie HungRe-arrange FD order
2020-01-01 Eddie HungMissing character
2020-01-01 Eddie HungDo not do call equiv_opt when no sim model exists
2020-01-01 Eddie HungFix warnings
2020-01-01 Eddie HungCall equiv_opt with -multiclock and -assert
2020-01-01 Eddie HungCleanup xilinx boxes
2020-01-01 Eddie HungCleanup ice40 boxes
2020-01-01 Eddie HungCleanup ecp5 boxes
2020-01-01 Eddie Hungparse_xaiger to not take box_lookup
2020-01-01 Eddie Hungparse_xaiger to reorder ports too
2020-01-01 Eddie HungAdd some abc9 dff tests
2020-01-01 Eddie HungDo not re-order carry chain ports, just precompute...
2019-12-31 Eddie HungUpdate abc9_xc7.box comments
2019-12-31 Eddie HungFDCE ports to be alphabetical
2019-12-31 Eddie HungFix attributes on $__ABC9_ASYNC[01] whitebox
2019-12-31 Eddie HungFix incorrect $__ABC9_ASYNC[01] box
2019-12-31 Eddie Hungwrite_xaiger: be more precise with ff_bits, remove...
2019-12-31 Eddie HungRetry getting rid of write_xaiger's holes_mode
2019-12-31 Eddie HungRevert "Get rid of holes_mode"
2019-12-31 Eddie HungGet rid of holes_mode
2019-12-31 Eddie HungAdd -D DFF_MODE to abc9_map test
2019-12-31 Eddie HungRemove delay targets doc
2019-12-30 Eddie Hungwrite_xaiger to use scratchpad for stats; cleanup abc9
2019-12-30 Eddie HungGrammar
2019-12-30 Eddie HungRemove submod changes
2019-12-30 Eddie HungUpdate timings for Xilinx S7 cells
2019-12-30 Eddie HungRemove unused
2019-12-30 Eddie HungDo not offset FD* box timings due to -46ps Tsu
2019-12-30 Eddie HungCall "proc" if processes inside whiteboxes
2019-12-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 Eddie HungAdd CHANGELOG entry, add abc9_{flop,keep} attr to README.md
2019-12-30 Eddie HungTidy up abc9_map.v
2019-12-30 Eddie HungAdd "synth_xilinx -dff" option, cleanup abc9
2019-12-30 Eddie HungUpdate doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 Eddie HungDisable synth_gowin -abc9 as it offers no advantages yet
2019-12-30 Eddie HungRevert "Revert "synth_* with -retime option now calls...
2019-12-30 Eddie HungRevert "ABC to call retime all the time"
2019-12-30 Eddie HungGrammar
2019-12-30 Miodrag MilanovićMerge pull request #1589 from YosysHQ/iopad_default
2019-12-30 Eddie HungMerge pull request #1599 from YosysHQ/eddie/retry_1588
2019-12-30 Eddie HungMerge pull request #1600 from YosysHQ/eddie/cleanup_ecp5
2019-12-28 Miodrag MilanovicFix new tests
2019-12-28 Miodrag MilanovicMerge remote-tracking branch 'origin/master' into iopad...
2019-12-28 Miodrag MilanovicMake test without iopads
2019-12-28 Miodrag MilanovicRevert "Fix xilinx tests, when iopads are default"
2019-12-28 Eddie HungUpdate resource count
2019-12-28 Eddie HungNitpick cleanup for ecp5
2019-12-28 Eddie HungAdd #1598 testcase
2019-12-28 Eddie Hungwrite_xaiger: inherit port ordering from original module
2019-12-28 Eddie HungRevert "Merge pull request #1598 from YosysHQ/revert...
2019-12-27 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-12-27 Eddie Hungwrite_xaiger: simplify c{i,o}_bits
2019-12-27 David ShahMerge pull request #1598 from YosysHQ/revert-1588-eddie...
2019-12-27 David ShahRevert "write_xaiger: only instantiate each whitebox...
2019-12-27 Eddie HungReally fix it!
2019-12-27 Eddie Hungwrite_xaiger: fix arrival times for non boxes
2019-12-25 Miodrag Milanovicfixed invalid char
2019-12-25 Marcin Kościelnickiiopadmap: Emit tristate buffers with const OE for some...
2019-12-25 Marcin KościelnickiMerge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
2019-12-25 Marcin KościelnickiMinor nit fixes
2019-12-23 Eddie HungAdd DSP cascade tests
2019-12-23 Eddie HungFix OPMODE for PCIN->PCOUT cascades in xc6s, check...
2019-12-23 Eddie HungFix CEA/CEB check
2019-12-23 Eddie HungFix checking CE[AB] and for direct connections
2019-12-23 Eddie HungSupport unregistered cascades for A and B inputs
2019-12-23 Eddie HungAdd DSP48A* PCOUT -> PCIN cascade support
2019-12-23 Marcin Kościelnickixilinx: Test our DSP48A/DSP48A1 simulation models.
2019-12-23 Eddie HungDisable clock domain partitioning in Yosys pass, let...
2019-12-23 Eddie Hungwrite_xaiger to opt instead of just clean whiteboxes
2019-12-22 Marcin Kościelnickixilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-21 Miodrag MilanovicAddressed review comments
2019-12-21 Miodrag Milanoviciopad no op for compatibility with old scripts
2019-12-21 Miodrag MilanovicFix xilinx tests, when iopads are default
2019-12-21 Miodrag MilanovicMake iopad option default for all xilinx flows
2019-12-20 Eddie HungMerge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
2019-12-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
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