yosys.git
2016-07-01 Clifford WolfMerge branch 'assert-limit'
2016-07-01 Clifford WolfReplaced "select -assert-limit" with -assert-max and...
2016-07-01 eshellkoAdded 'assert-limit' option for 'select' command
2016-06-30 Clifford WolfImproved ice40_ffinit error reporting
2016-06-21 Clifford WolfMerge pull request #181 from rubund/input_logic_allowed
2016-06-20 Ruben UndheimAllow defining input ports as "input logic" in SystemVe...
2016-06-19 Clifford WolfBugfix in "abc -script" handling
2016-06-19 Clifford WolfMerge branch 'sv_packages' of https://github.com/rubund...
2016-06-19 Clifford WolfAdded "deminout"
2016-06-18 Ruben UndheimA few modifications after pull request comments
2016-06-18 Clifford WolfAdded "read_blif -sop"
2016-06-18 Clifford WolfAdded $sop support to BLIF back-end
2016-06-18 Ruben UndheimAdded support for SystemVerilog packages with localpara...
2016-06-17 Clifford WolfAdded "dc2" to default ABC scripts
2016-06-17 Clifford WolfFixed init issue in mem2reg_test2 test case
2016-06-17 Clifford WolfAdded "abc -I <num> -P <num>"
2016-06-17 Clifford WolfAdded $sop SAT model
2016-06-17 Clifford WolfImproved support for $sop cells
2016-06-17 Clifford WolfAdded $sop cell type and "abc -sop"
2016-06-17 Clifford WolfUpdated ABC to hg rev b5df6e2b76f0
2016-06-09 Clifford WolfAdded "nlutmap -assert"
2016-06-08 Clifford WolfDo not run "wreduce" in "prep -ifx"
2016-06-06 Clifford WolfAdded "proc_mux -ifx"
2016-06-03 Clifford WolfAdded "setundef -init"
2016-06-02 Clifford WolfFix all undef-muxes in dlatch input cone
2016-06-01 Clifford WolfAvoid creating undef-muxes when inferring latches in...
2016-05-29 Clifford WolfAdded opt_expr support for div/mod by power-of-two
2016-05-27 Clifford WolfFixed procedural assignments to non-unique lvalues...
2016-05-27 Clifford WolfFixed access-after-delete bug in mem2reg code
2016-05-27 Clifford Wolffixed typos in error messages
2016-05-27 Clifford WolfFixed "scc" for cells that have feedback singals _and_...
2016-05-22 Clifford WolfMerge pull request #172 from zeldin/deterministic_hierarchy
2016-05-22 Marcus ComstedtMade the expansion order of hierarchy deterministic
2016-05-20 Clifford WolfSome fixes in tests/asicworld/*_tb.v
2016-05-20 Clifford WolfImprovements and fixes in autotest.sh script and test_a...
2016-05-20 Clifford WolfMerge branch 'master' of https://github.com/Kmanfi...
2016-05-20 Clifford WolfAlso escape "=" in spice output
2016-05-20 Clifford WolfSmall improvements in Verilog front-end docs
2016-05-19 Kaj TuomiClose opened dump file.
2016-05-19 Kaj TuomiFix for Modelsim transcript line warp issue #164
2016-05-14 Clifford WolfDon't sign-extend memory bram initialization data
2016-05-14 Clifford WolfAdded missing "#define HASHLIB_H"
2016-05-14 Clifford WolfMinor presentation fixes
2016-05-11 Clifford WolfUpdated min GCC requirement to GCC 4.8
2016-05-09 Clifford WolfAdded manual download link to README
2016-05-08 Clifford WolfInclude <cmath> in yosys.h
2016-05-08 Clifford WolfMerge pull request #162 from azonenberg/master
2016-05-08 Andrew ZonenbergAdded GP_DELAY cell
2016-05-08 Andrew ZonenbergFixed typo in port name
2016-05-08 Andrew ZonenbergFixed extra semicolon
2016-05-08 Andrew ZonenbergFixed typo in parameter name
2016-05-08 Andrew ZonenbergAdded simulation timescale declaration
2016-05-07 Clifford WolfFixes for MXE build
2016-05-07 Clifford WolfAdded support for "keep" attribute to shregmap
2016-05-06 Clifford WolfAdded synth_ice40 support for latches via logic loops
2016-05-06 Clifford WolfAdded "write_blif -noalias"
2016-05-06 Clifford WolfFixed ice40_opt lut unmapping, added "ice40_opt -unlut"
2016-05-06 Clifford WolfFixed preservation of important attributes in techmap
2016-05-05 Clifford WolfMerge pull request #159 from azonenberg/master
2016-05-05 Andrew ZonenbergChanged order of passes for better handling of INIT...
2016-05-05 Andrew ZonenbergChanged port names in greenpak shregmap
2016-05-05 Andrew ZonenbergRenamed module parameter
2016-05-04 Andrew ZonenbergRefactored synth_greenpak4 to use iopadmap for mapping...
2016-05-04 Clifford WolfAdded tristate buffer support to iopadmap
2016-05-04 Clifford WolfMerge pull request #157 from azonenberg/master
2016-05-04 Andrew ZonenbergFixed incorrect signal naming in GP_IOBUF
2016-05-04 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-05-04 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-05-04 Clifford WolfFixed iopadmap attribute handling
2016-05-04 Andrew ZonenbergAdded tri-state I/O extraction for GreenPak
2016-05-04 Andrew ZonenbergAdded GreenPak I/O buffer cells
2016-05-03 Andrew ZonenbergAdded comment to clarify GP_ABUF cell
2016-05-03 Andrew ZonenbergAdded GP_ABUF cell
2016-05-02 Clifford WolfMerge pull request #154 from azonenberg/master
2016-05-01 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-29 Clifford WolfImproved TCL_VERSION detection so it does not read...
2016-04-29 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-28 Clifford WolfAdded "qwp -v"
2016-04-28 Andrew ZonenbergAdded GP_PGA cell
2016-04-26 Clifford WolfConnections between inputs and inouts are driven by...
2016-04-25 Clifford WolfFixed test_autotb for modules with many cell ports
2016-04-25 Clifford WolfFixed proc_mux performance bug
2016-04-25 Clifford WolfMerge pull request #150 from azonenberg/master
2016-04-25 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-25 Andrew ZonenbergRemoved VIN_BUF_EN
2016-04-24 Clifford WolfFixed performance bug in proc_dlatch
2016-04-24 Clifford WolfAdded "yosys -D ALL"
2016-04-24 Andrew ZonenbergRenamed VOUT to OUT on GP_ACMP cell
2016-04-24 Andrew ZonenbergAdded GP_ACMP cell
2016-04-23 Clifford WolfAdded "prep -flatten" and "synth -flatten"
2016-04-23 Clifford WolfConverted "prep" to ScriptPass
2016-04-23 Clifford WolfImprovements in greenpak4 shreg mapping
2016-04-23 Clifford WolfRun clean after splitnets in synth_greenpak4
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-23 Clifford WolfAdded "shregmap -zinit" for greenpak4 tech
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-23 Clifford WolfMerge https://github.com/azonenberg/yosys
2016-04-23 Clifford WolfAdded "shregmap" to synth_greenpak4
2016-04-23 Clifford WolfConverted synth_greenpak4 to ScriptPass
2016-04-23 Andrew ZonenbergFixed typo in help text
next