yosys.git
2019-03-23 Eddie HungLeftover printf
2019-03-23 Eddie HungFixes for multibit
2019-03-23 Eddie HungWorking for 1 bit
2019-03-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 Clifford WolfMerge pull request #889 from YosysHQ/clifford/fix888
2019-03-22 Clifford WolfMerge pull request #890 from YosysHQ/clifford/fix887
2019-03-22 David ShahMerge pull request #891 from YosysHQ/xilinx_keep
2019-03-22 David Shahxilinx: Add keep attribute where appropriate
2019-03-22 Clifford WolfTrim init attributes when resizing FFs in "wreduce...
2019-03-21 Eddie HungAdd '-nosrl' option to synth_xilinx
2019-03-21 Clifford WolfFix mem2reg handling of memories with upto data ports...
2019-03-21 Clifford WolfImprove "read_verilog -dump_vlog[12]" handling of upto...
2019-03-21 Clifford WolfImprove read_verilog debug output capabilities
2019-03-21 Eddie HungOpt
2019-03-20 Eddie HungFix spacing
2019-03-20 Eddie HungFine tune cells_map.v
2019-03-20 Eddie HungRevert $__SHREG_ to orig; use $__XILINX_SHREG for varia...
2019-03-20 Eddie HungAdd support for variable length Xilinx SRL > 128
2019-03-19 Eddie HungRestore original synth_xilinx commands
2019-03-19 Eddie HungFix spacing
2019-03-19 Eddie Hungshregmap -tech xilinx to delete $shiftx for var length SRL
2019-03-19 Eddie HungFix INIT for variable length SRs that have been bumped...
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 Eddie HungMake output port a non chain user
2019-03-19 Clifford WolfMerge pull request #885 from YosysHQ/clifford/fix873
2019-03-19 Clifford WolfAdd Xilinx negedge FFs to synth_xilinx dffinit call...
2019-03-19 Eddie HungMerge pull request #808 from eddiehung/read_aiger
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-19 Eddie HungAdd author name
2019-03-19 Clifford WolfMerge pull request #884 from zachjs/master
2019-03-19 Zachary Snowfix local name resolution in prefix constructs
2019-03-18 Eddie HungFix shregmap to correctly recognise non chain users...
2019-03-18 Eddie Hungshiftx NULL pointer check
2019-03-17 Clifford WolfUpdate issue template
2019-03-17 Clifford WolfUpdate issue template
2019-03-16 Eddie HungCleanup
2019-03-16 Eddie HungOnly accept <128 for variable length, only if $shiftx...
2019-03-16 Clifford WolfMerge pull request #877 from FelixVi/master
2019-03-16 Felix VietmeyerAdd note about test requirements in README
2019-03-16 Eddie HungCleanup synth_xilinx
2019-03-16 Eddie HungWorking
2019-03-15 Clifford WolfImprove mix of src/wire/wirebit coverage in "mutate...
2019-03-15 Clifford WolfMerge pull request #876 from YosysHQ/clifford/fmcombine
2019-03-15 Clifford WolfAdd "fmcombine -fwd -bwd -nop"
2019-03-15 Clifford WolfAdd fmcombine pass
2019-03-14 Clifford WolfMerge pull request #875 from YosysHQ/clifford/mutate
2019-03-14 Clifford WolfDisable realmath tests
2019-03-14 Clifford WolfImprovements in "mutate" list-reduce algorithm
2019-03-14 Clifford WolfAdd "mutate -cfg", improve pick_cover behavior
2019-03-14 Clifford WolfAdd a strictly coverage-driven mutation selection strategy
2019-03-14 Clifford WolfImprove "mutate" wire coverage metric
2019-03-14 Clifford WolfAdd more mutation types, improve mutation src cover
2019-03-14 Clifford WolfFix smtbmc.py handling of zero appended steps
2019-03-14 Clifford WolfAdd "mutate" command DB reduce functionality
2019-03-14 Clifford WolfAdd hashlib "<container>::element(int n)" methods
2019-03-14 Clifford WolfAdd "mutate -mode inv", various other mutate improvements
2019-03-14 Clifford WolfAdd basic "mutate -list N" framework
2019-03-14 Clifford WolfMerge pull request #874 from YosysHQ/clifford/andopt
2019-03-14 Clifford WolfImprove handling of and-with-1 and or-with-0 in opt_exp...
2019-03-14 Clifford WolfMerge pull request #872 from YosysHQ/clifford/pmuxfix
2019-03-14 Clifford WolfImprove handling of "full_case" attributes
2019-03-14 Clifford WolfFix a syntax bug in ilang backend related to process...
2019-03-14 Eddie HungReverse bits in INIT parameter for Xilinx, since MSB...
2019-03-14 Eddie HungMisspell
2019-03-14 Eddie HungRevert "Add shregmap -init_msb_first and use in synth_x...
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 Clifford WolfMerge pull request #869 from cr1901/win-shell
2019-03-14 Eddie HungAdd shregmap -init_msb_first and use in synth_xilinx
2019-03-14 Eddie HungFix cells_map for SRL
2019-03-14 Eddie HungMove shregmap until after first techmap
2019-03-13 Eddie HungRefactor $__SHREG__ in cells_map.v
2019-03-13 William D.... Install launcher executable when running yosys-smtbmc...
2019-03-13 Clifford WolfMerge pull request #868 from YosysHQ/clifford/fixmem
2019-03-12 Clifford WolfFix a bug in handling quotes in multi-cmd lines in...
2019-03-12 Clifford WolfMerge pull request #866 from YosysHQ/clifford/idstuff
2019-03-12 Clifford WolfRemove ice40/cells_sim.v hack to avoid warning for...
2019-03-12 Clifford WolfImprove handling of memories used in mem index expressi...
2019-03-12 Clifford WolfRemove outdated "blocking assignment to memory" warning
2019-03-12 Clifford WolfOnly set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for...
2019-03-11 Clifford WolfImprove determinism of IdString DB for similar scripts
2019-03-11 Eddie HungMerge pull request #864 from YosysHQ/svalabelfix
2019-03-11 Clifford WolfAdd ENABLE_GLOB Makefile switch
2019-03-10 Clifford WolfFix handling of cases that look like sva labels, fixes...
2019-03-09 Clifford WolfFix typo in ice40_braminit help msg
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-09 Clifford WolfFix signed $shift/$shiftx handling in write_smt2
2019-03-09 Clifford WolfAdd $dffsr support to async2sync
2019-03-09 Clifford WolfMerge pull request #858 from YosysHQ/clifford/svalabels
2019-03-09 Clifford WolfMerge pull request #861 from YosysHQ/verific_chparam
2019-03-09 Clifford WolfAlso add support for labels on sva module items, fixes...
2019-03-09 Eddie HungUpdate help message for -chparam
2019-03-09 Eddie HungAdd -chparam option to verific command
2019-03-09 Eddie HungFix spelling
2019-03-08 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2019-03-08 Clifford WolfFix handling of task output ports in clocked always...
2019-03-07 Sylvain Munautice40: Run ice40_braminit pass by default
2019-03-07 Sylvain Munautice40: Add ice40_braminit pass to allow initialization...
2019-03-07 Clifford WolfMerge pull request #856 from kprasadvnsi/master
2019-03-07 Clifford WolfUse SVA label in smt export if available
2019-03-07 Clifford WolfAdd support for SVA labels in read_verilog
next