yosys.git
2021-06-16 Ashton SnelgroveInclude blif reader header in public facing extension...
2021-06-14 Xiretzaverilog: fix leaking of type names in parser
2021-06-14 Xiretzaverilog: fix wildcard port connections leaking memory
2021-06-14 Xiretzaast: delete wires and localparams after finishing const...
2021-06-14 Xiretzaverilog: fix leaking ASTNodes
2021-06-14 Xiretzaast: fix error condition causing assert to fail
2021-06-14 Zachary Snowmacos: fix leak in proc_self_dirname()
2021-06-14 Rupert SwarbrickSimplify some RTLIL destructors
2021-06-14 Marcelina Kościelnickaverilog: Squash a memory leak.
2021-06-11 Marcelina KościelnickaAdd regression test for #2824.
2021-06-11 gatecatopt_muxtree: Update port_off and port_idx even for...
2021-06-09 Marcelina Kościelnickaopt_expr: Fix mul/div/mod by POT patterns to support...
2021-06-09 Marcelina Kościelnickaopt_expr: Optimize div/mod by const 1.
2021-06-09 Claire XenMerge pull request #2817 from YosysHQ/claire/fixemails
2021-06-09 Claire Xenia... Fix deadname SVN links
2021-06-09 Claire Xenia... Intersynth URL
2021-06-09 Claire Xenia... More deadname stuff
2021-06-09 Claire Xenia... Fix icestorm links
2021-06-09 Claire Xenia... More deadname stuff
2021-06-09 Claire Xenia... Use HTTPS for website links, gatecat email
2021-06-09 Claire Xenia... Fix files with CRLF line endings
2021-06-08 Zachary Snowverilog: check for module scope identifiers during...
2021-06-08 Zachary Snowmem2reg: tolerate out of bounds constant accesses
2021-06-08 Zachary Snowautoname: simple perf optimizations
2021-06-07 Claire Xenia... Fixing old e-mail addresses and deadnames
2021-06-07 Claire Xenia... Add claire deadname stuff to .mailmap
2021-06-01 Zachary Snowsv: support tasks and functions within packages
2021-06-01 Marcelina Kościelnickakernel/mem: Recognize some deprecated memory port configs.
2021-05-31 Marcelina Kościelnickamemory_map: Improve start_offset handling.
2021-05-29 Marcelina Kościelnickamemory_share: Add read port merging.
2021-05-28 Marcelina Kościelnickamemory_share: Improve sat-based port sharing.
2021-05-27 Marcelina KościelnickaMake a few passes auto-call Mem::narrow instead of...
2021-05-27 Marcelina Kościelnickabackends/verilog: Add support for memory read port...
2021-05-27 Marcelina Kościelnickabackends/verilog: Add wide port support.
2021-05-27 Marcelina Kościelnickamemory_share: Improve same-address merging, recognize...
2021-05-27 Marcelina Kościelnickakernel/mem: Add helpers for write port widening.
2021-05-26 Marcelina Kościelnickakernel/mem: Add sub_addr helpers.
2021-05-26 Marcelina Kościelnickakernel/mem: Add prepare_wr_merge helper.
2021-05-25 Marcelina Kościelnickabackends/verilog: Try to preserve mem write port priori...
2021-05-25 Marcelina Kościelnickamem/extract_rdff: Fix "no FF made" edge case.
2021-05-25 Marcelina Kościelnickamemory_bram: Reuse extract_rdff helper for make_outreg.
2021-05-25 Zachary Snowverilog: fix case expression sign and width handling
2021-05-25 Zachary Snowsv: support remaining assignment operators
2021-05-25 Marcelina Kościelnickamem/extract_rdff: Add alternate transparency handling.
2021-05-25 Marcelina Kościelnickaopt_mem: Add reset/init value support.
2021-05-25 Marcelina Kościelnickakernel/mem: Add model support for read port init value...
2021-05-25 Marcelina Kościelnickamem/extract_rdff: Fix wire naming and wide port support.
2021-05-25 Marcelina Kościelnickamemory_bram: Respect write port priority.
2021-05-25 Marcelina Kościelnickaopt_mem_feedback: Respect write port priority.
2021-05-25 Marcelina Kościelnickakernel/mem: Add emulate_priority helper.
2021-05-25 Marcelina KościelnickaAdd memory_narrow pass.
2021-05-25 Marcelina Kościelnickamemory_share: Add wide port support.
2021-05-25 Marcelina Kościelnickaopt_mem_feedback: Add wide port support.
2021-05-25 Marcelina Kościelnickamemory_map: Add wide port support.
2021-05-25 Marcelina Kościelnickasim: Add wide port support.
2021-05-25 Marcelina KościelnickaReject wide ports in some passes that will never suppor...
2021-05-25 Marcelina Kościelnickakernel/mem: Add a Mem::narrow helper to split up wide...
2021-05-25 Marcelina Kościelnickakernel/mem: Emit support for wide ports in packed mode.
2021-05-25 Marcelina Kościelnickakernel/mem: Add model for wide ports.
2021-05-24 Marcelina Kościelnickakernel/mem: Add priority_mask to model.
2021-05-24 Marcelina Kościelnickaopt_mem_feedback: Rewrite feedback path finding logic.
2021-05-24 Marcelina Kościelnickaopt_mem_feedback: Convert to Mem helpers.
2021-05-24 Marcelina Kościelnickahashlib: Add a hash for bool.
2021-05-24 Marcelina KościelnickaAdd a .mailmap file.
2021-05-24 Miodrag MilanovićMerge pull request #2779 from YosysHQ/mwk/nuke-travis
2021-05-24 Marcelina KościelnickaRemove Travis CI.
2021-05-24 Marcelina Kościelnickabackend/firrtl: Convert to use Mem helpers.
2021-05-24 Marcelina Kościelnickagithub actions: Test on several gcc and clang versions...
2021-05-23 Marcelina Kościelnickamemory_share: Use Mem helpers.
2021-05-23 Marcelina Kościelnickaextract_rdff: Add initvals parameter.
2021-05-23 Marcelina Kościelnickabtor: Use is_mem_cell in one more place.
2021-05-23 Marcelina Kościelnickamemory_share: Split off feedback path finding as a...
2021-05-23 Marcelina KościelnickaAdd new helper class for merging FFs into cells, use...
2021-05-23 Marcelina Kościelnickaopt_mem: Remove write ports with const-0 EN.
2021-05-22 Marcelina Kościelnickamemory_memx: Use Mem helper.
2021-05-22 Marcelina Kościelnickakernel/rtlil: Extract some helpers for checking memory...
2021-05-22 Marcelina Kościelnickakernel/mem: Add a check() function.
2021-05-22 Marcelina Kościelnickakernel/mem: defer port removal to emit()
2021-05-21 Marcelina Kościelnickamemory_dff: Use Mem helper.
2021-05-20 Miodrag MilanovićRun VS build on PRs and each push
2021-05-20 Marcelina KościelnickaBump version
2021-05-20 Marcelina Kościelnickatests/blif: Add missing gitignore
2021-05-17 Miodrag MilanovicVisual Studio build action
2021-05-15 gatecatintel_alm: Fix illegal carry chains
2021-05-15 gatecatintel_alm: Add global buffer insertion
2021-05-15 gatecatintel_alm: Add IO buffer insertion
2021-05-14 Rupert SwarbrickChange the type of current_module to Module
2021-05-14 Rupert SwarbrickUse range-based for loop in AST::process
2021-05-12 Adam GreigAdd missing parameters for MULT18X18D and ALU54B to...
2021-05-10 Zachary Snowsv: check validity of package end label
2021-05-08 Marcelina Kościelnickablif: Use library cells' start_offset and upto for...
2021-05-08 Marcelina Kościelnickaconnect: Add -assert option, fix non-working sigmap.
2021-05-04 Marcelina Kościelnickaopt_dff: Fix NOT gates wired in reverse.
2021-04-27 Miodrag MilanovićMerge pull request #2738 from mdko/xilinx-blif
2021-04-27 Michael ChristensenFix use of blif name in synth_xilinx command
2021-04-26 Claire XenMerge pull request #2737 from YosysHQ/claire/fix2736
2021-04-26 Claire Xenia... Remove duplicates from conns array in JSON front-end...
2021-04-21 Claire XenMerge pull request #2669 from YosysHQ/claire/ice40defaults
2021-04-20 Claire Xenia... Add default assignments to other SB_* simulation models
2021-04-20 Claire Xenia... Add default assignments to SB_LUT4
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