yosys.git
2019-07-18 Eddie Hungice40_dsp to accept $__MUL16X16 too
2019-07-18 Eddie Hungsynth_ice40 to decompose into 16x16
2019-07-18 Eddie Hungmul2dsp to create cells that can be interchanged with...
2019-07-18 Eddie HungCheck if RHS is empty first
2019-07-18 Eddie HungMake consistent
2019-07-18 Eddie HungDo not autoremove ffP aor muxP
2019-07-18 Eddie HungImprove pattern matcher to match subsets of $dffe?...
2019-07-18 Eddie HungImprove A/B reg packing
2019-07-18 Eddie HungDo not autoremove A/B registers since they might have...
2019-07-18 Eddie HungFix xilinx_dsp index cast
2019-07-18 Eddie HungFix signed multiplier decomposition
2019-07-18 Eddie HungUse single DSP_SIGNEDONLY macro
2019-07-18 Eddie HungWorking for unsigned
2019-07-18 Eddie HungCleanup
2019-07-18 Eddie HungWrong wildcard symbol
2019-07-18 Eddie HungMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
2019-07-18 David Shahmul2dsp: Lower partial products always have unsigned...
2019-07-17 Eddie HungMake all operands signed
2019-07-17 Eddie HungUpdate comment
2019-07-17 Eddie HungPattern matcher to check pool of bits, not exactly
2019-07-17 Eddie HungFix mul2dsp signedness
2019-07-17 Eddie HungA_SIGNED == B_SIGNED so flip both
2019-07-17 Eddie HungSigSpec::remove_const() to return SigSpec&
2019-07-16 Eddie HungAdd DSP_{A,B}_SIGNEDONLY macro
2019-07-16 Eddie HungSignedness
2019-07-16 Eddie HungSigned extension
2019-07-16 Eddie HungRevert drop down to 24x16 multipliers for all
2019-07-16 Eddie HungMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
2019-07-16 Eddie HungAdd support {A,B,P}REG packing
2019-07-16 Eddie HungSigSpec::extract to allow negative length
2019-07-16 Eddie HungAdd support for {A,B,P}REG in DSP48E1
2019-07-16 David Shahxilinx: Add correct signed behaviour to DSP48E1 model
2019-07-16 David Shahxilinx: Treat DSP48E1 as 24x17 unsigned for now (actual...
2019-07-16 David Shahmul2dsp: Fix edge case where Y_WIDTH is less than B_WID...
2019-07-16 David Shahmul2dsp: Fix indentation
2019-07-15 Eddie HungDo not swap if equals
2019-07-15 Eddie HungSigSpec::extend_u0() to return *this
2019-07-15 Eddie HungOops forgot these files
2019-07-15 Eddie HungAdd xilinx_dsp for register packing
2019-07-15 Eddie HungOUT port to Y in generic DSP
2019-07-15 Eddie HungMove DSP mapping back out to dsp_map.v
2019-07-15 Eddie HungOnly swap if B_WIDTH > A_WIDTH
2019-07-15 Eddie HungTidy up
2019-07-15 Eddie HungMove DSP48E1 model out of cells_xtra, initial multiply...
2019-07-15 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-07-14 Eddie HungMerge pull request #1194 from cr1901/miss-semi
2019-07-14 William D.... Fix missing semicolon in Windows-specific code in aiger...
2019-07-12 Clifford WolfMerge pull request #1183 from whitequark/ice40-always...
2019-07-11 whitequarksynth_ice40: switch -relut to be always on.
2019-07-11 whitequarksynth_ice40: fix help text typo. NFC.
2019-07-11 Eddie HungMerge pull request #1182 from koriakin/xc6s-bram
2019-07-11 Eddie HungMerge pull request #1185 from koriakin/xc-ff-init-vals
2019-07-11 Marcin Kościelnickixilinx: Fix the default values for FDPE/FDSE INIT attri...
2019-07-11 Eddie HungEnable &mfs for abc9, even if it only currently works...
2019-07-11 Marcin Kościelnickisynth_xilinx: Initial Spartan 6 block RAM inference...
2019-07-11 Clifford WolfMerge pull request #1172 from whitequark/write_verilog...
2019-07-11 Clifford WolfMerge pull request #1179 from whitequark/attrmap-proc
2019-07-10 Eddie HungMove dsp_map.v into cells_map.v; cleanup synth_xilinx...
2019-07-10 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-07-10 Eddie HungMerge pull request #1180 from YosysHQ/eddie/no_abc9_retime
2019-07-10 Eddie HungMerge pull request #1148 from YosysHQ/xc7mux
2019-07-10 Eddie HungError out if -abc9 and -retime specified
2019-07-10 Eddie HungAdd some spacing
2019-07-10 Eddie HungAdd some ASCII art explaining mux decomposition
2019-07-10 whitequarkattrmap: also consider process, switch and case attributes.
2019-07-10 Clifford WolfMerge pull request #1177 from YosysHQ/clifford/async
2019-07-10 Eddie HungCall muxpack and pmux2shiftx before cmp2lut
2019-07-09 Eddie HungRestore opt_clean back to original place
2019-07-09 Eddie HungRestore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
2019-07-09 David Shahsynth_ecp5: Fix typo in copyright header
2019-07-09 Clifford WolfMerge pull request #1174 from YosysHQ/eddie/fix1173
2019-07-09 Clifford WolfMerge pull request #1175 from whitequark/write_verilog...
2019-07-09 Clifford WolfFix tests/various/async FFL test
2019-07-09 Clifford WolfImprove tests/various/async, disable failing ffl test
2019-07-09 Eddie HungExtend using A[1] to preserve don't care
2019-07-09 Eddie HungMerge pull request #1171 from YosysHQ/revert-1166-eddie...
2019-07-09 Eddie HungMerge remote-tracking branch 'origin/eddie/fix1173...
2019-07-09 whitequarkwrite_verilog: fix placement of case attributes. NFC.
2019-07-09 Eddie HungIncrement _TECHMAP_BITS_CONNMAP_ by one since counting...
2019-07-09 Clifford WolfAdd tests/various/async.{sh,v}
2019-07-09 Clifford WolfImprove tests/various/run-test.sh
2019-07-09 Clifford WolfAdd tests/simple_abc9/.gitignore
2019-07-09 whitequarkwrite_verilog: write RTLIL::Sa aka - as Verilog ?.
2019-07-09 Eddie HungExtend during mux decomposition with 1'bx
2019-07-09 Eddie HungFix typo and comments
2019-07-09 Eddie HungMerge pull request #1170 from YosysHQ/eddie/fix_double_...
2019-07-09 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-07-09 Eddie Hungsynth_xilinx to call commands of synth -coarse directly
2019-07-09 Eddie HungRevert "synth_xilinx to call "synth -run coarse" with...
2019-07-09 Eddie HungRevert "Add "synth -keepdc" option"
2019-07-09 Eddie HungRename __builtin_bswap32 -> bswap32
2019-07-09 Eddie HungFix spacing
2019-07-09 Eddie HungFix spacing
2019-07-09 Clifford WolfMerge pull request #1168 from whitequark/bugpoint-processes
2019-07-09 Clifford WolfMerge pull request #1169 from whitequark/more-proc...
2019-07-09 Clifford WolfMerge pull request #1163 from whitequark/more-case...
2019-07-09 Clifford WolfMerge pull request #1162 from whitequark/rtlil-case...
2019-07-09 Clifford WolfMerge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
2019-07-09 whitequarkproc_prune: promote assigns to module connections when...
2019-07-09 whitequarkproc_prune: new pass.
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