yosys.git
2019-05-03 Eddie HungAdd quick-and-dirty specify tests
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-05-03 Eddie HungRename cells_map.v to prevent clash with ff_map.v
2019-05-03 Eddie Hungiverilog with simcells.v as well
2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff
2019-05-03 Clifford WolfMerge pull request #984 from YosysHQ/eddie/fix_982
2019-05-03 Eddie HungRevert "synth_xilinx to call dffinit with -noreinit"
2019-05-03 Eddie HungIf init is 1'bx, do not add to dict as per @cliffordwolf
2019-05-03 Eddie HungRevert "dffinit -noreinit to silently continue when...
2019-05-03 Clifford WolfMerge pull request #976 from YosysHQ/clifford/fix974
2019-05-03 Clifford WolfMerge pull request #985 from YosysHQ/clifford/fix981
2019-05-03 Clifford WolfFix typo in tests/svinterfaces/runone.sh
2019-05-03 Clifford WolfMerge pull request #979 from jakobwenzel/svinterfacesTe...
2019-05-03 Clifford WolfImprove opt_expr and opt_clean handling of (partially...
2019-05-03 Clifford WolfUpdate pmgen documentation
2019-05-03 Clifford WolfFix typo
2019-05-03 Eddie Hungsynth_xilinx to call dffinit with -noreinit
2019-05-03 Eddie Hungdffinit -noreinit to silently continue when init value...
2019-05-02 Jakob Wenzelfail svinterfaces testcases on yosys error exit
2019-05-02 Clifford WolfMerge pull request #963 from YosysHQ/eddie/synth_xilinx...
2019-05-02 Eddie HungMerge pull request #978 from ucb-bar/fmtfirrtl
2019-05-02 Eddie HungBack to passing all xc7srl tests!
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-05-01 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-05-01 Jim LawsonRe-indent firrtl.cc:struct memory - no functional change.
2019-05-01 Clifford WolfMerge branch 'clifford/fix883'
2019-05-01 Clifford WolfAdd missing enable_undef to "sat -tempinduct-def",...
2019-05-01 Clifford WolfMerge pull request #977 from ucb-bar/fixfirrtlmem
2019-05-01 Jim LawsonFix #938 - Crash occurs in case when use write_firrtl...
2019-05-01 Clifford WolfFix floating point exception in qwp, fixes #923
2019-05-01 Clifford WolfAdd splitcmplxassign test case and silence splitcmplxas...
2019-05-01 Clifford WolfFix width detection of memory access with bit slice...
2019-04-30 Clifford WolfFix segfault in wreduce
2019-04-30 Clifford WolfDisabled "final loop assignment" feature
2019-04-30 Clifford WolfMerge pull request #972 from YosysHQ/clifford/fix968
2019-04-30 Clifford WolfMerge pull request #966 from YosysHQ/clifford/fix956
2019-04-30 Clifford WolfMerge pull request #962 from YosysHQ/eddie/refactor_syn...
2019-04-30 Clifford WolfMerge branch 'master' into eddie/refactor_synth_xilinx
2019-04-30 Clifford WolfMerge pull request #973 from christian-krieg/feature...
2019-04-30 Clifford WolfInclude filename in "Executing Verilog-2005 frontend...
2019-04-30 Clifford WolfFix performance bug in RTLIL::SigSpec::operator==(...
2019-04-30 Clifford WolfAdd final loop variable assignment when unrolling for...
2019-04-30 Clifford WolfAdd handling of init attributes in "opt_expr -undriven"
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-30 Benedikt TutzerCleaned up root directory
2019-04-30 Clifford WolfAdd peepopt_muldiv, fixes #930
2019-04-30 Clifford Wolfpmgen progress
2019-04-30 Clifford WolfRun "peepopt" in generic "synth" pass and "synth_ice40"
2019-04-30 Clifford WolfSome pmgen reorg, rename peepopt.pmg to peepopt_shiftmu...
2019-04-30 Clifford WolfProgress in shiftmul peepopt pattern
2019-04-29 Clifford WolfMerge pull request #960 from YosysHQ/eddie/equiv_opt_undef
2019-04-29 Clifford WolfMerge pull request #967 from olegendo/depfile_esc_spaces
2019-04-29 Clifford WolfAdd "peepopt" skeleton
2019-04-29 Clifford WolfAdd pmgen support for multiple patterns in one matcher
2019-04-29 Oleg Endofix codestyle formatting
2019-04-29 Clifford WolfSupport multiple pmg files (right now just concatenated...
2019-04-29 Oleg Endoescape spaces with backslash when writing dep file
2019-04-29 Clifford WolfDrive dangling wires with init attr with their init...
2019-04-28 Eddie HungCopy with 1'bx padding in $shiftx
2019-04-28 Eddie HungWIP
2019-04-28 Eddie HungMove neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-04-26 Eddie HungRevert synth_xilinx 'fine' label more to how it used...
2019-04-26 Eddie HungWhere did this check come from!?!
2019-04-26 Eddie HungRefactor synth_xilinx to auto-generate doc
2019-04-26 Eddie HungCleanup ice40
2019-04-26 Eddie HungAdd -undef option to equiv_opt, passed to equiv_induct
2019-04-25 Eddie HungMisspelling
2019-04-23 Clifford WolfAdd specify support to README
2019-04-23 Clifford WolfImprove $specrule interface
2019-04-23 Clifford WolfImprove $specrule interface
2019-04-23 Clifford WolfAdd $specrule cells for $setup/$hold/$skew specify...
2019-04-23 Clifford WolfPreserve $specify[23] cells
2019-04-23 Clifford WolfAllow $specify[23] cells in blackbox modules
2019-04-23 Clifford WolfRename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better...
2019-04-23 Clifford WolfAdd $specify2/$specify3 support to write_verilog
2019-04-23 Clifford WolfAdd support for $assert/$assume/$cover to write_verilog
2019-04-23 Clifford WolfAdd CellTypes support for $specify2 and $specify3
2019-04-23 Clifford WolfAdd InternalCellChecker support for $specify2 and ...
2019-04-23 Clifford WolfChecking and fixing specify cells in genRTLIL
2019-04-23 Clifford WolfUn-break default specify parser
2019-04-23 Clifford WolfAdd specify parser
2019-04-23 Clifford WolfAdd $specify2 and $specify3 cells to simlib
2019-04-23 Clifford WolfMerge pull request #957 from YosysHQ/oai4fix
2019-04-23 David ShahFixes for OAI4 cell implementation
2019-04-23 Eddie HungFormat some names using inline code
2019-04-23 Eddie HungFix spelling
2019-04-23 Clifford WolfRemove some left-over log_dump()
2019-04-22 Eddie HungMerge pull request #914 from YosysHQ/xc7srl
2019-04-22 Eddie HungUpdate help message
2019-04-22 Clifford WolfMerge pull request #952 from YosysHQ/clifford/fix370
2019-04-22 Clifford WolfMerge pull request #951 from YosysHQ/clifford/logdebug
2019-04-22 Clifford WolfMerge pull request #949 from YosysHQ/clifford/pmux2shim...
2019-04-22 Clifford WolfMerge pull request #953 from YosysHQ/clifford/fix948
2019-04-22 Eddie HungMove 'shregmap -tech xilinx' into map_cells
2019-04-22 Clifford WolfAdd support for zero-width signals to Verilog back...
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 Clifford WolfDetermine correct signedness and expression width in...
2019-04-22 Clifford WolfAdd log_debug() framework
2019-04-22 Clifford WolfMerge pull request #950 from whitequark/attrmap_remove_...
2019-04-22 whitequarkattrmap: extend -remove to allow removing attributes...
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