litex.git
2015-10-19 Sebastien Bourdeauducqverilog, sim: accept iterables in FHDL statements
2015-10-19 Sebastien Bourdeauducqgenlib/fsm: fix return value of _get_register_control
2015-10-19 Sebastien BourdeauducqRevert "sim/core: fix Cat bitshift"
2015-10-19 Sebastien Bourdeauducqsim/core: fix Cat bitshift
2015-10-19 Sebastien Bourdeauducqsim/core: truncate evaluated values before test in If
2015-10-19 Sebastien Bourdeauducqbuild/vivado: quote paths in Tcl (prevents problems...
2015-10-15 Sebastien Bourdeauducqsim: support execution of nested statement lists (typo)
2015-10-15 Sebastien Bourdeauducqsim: support execution of nested statement lists
2015-10-14 Sebastien Bourdeauducqgenlib/fifo: width_or_layout -> width
2015-10-13 Sebastien Bourdeauducqtest/divider: subtests
2015-10-05 Sebastien Bourdeauducqsim: make sure replaced memory signals are always in...
2015-10-04 Sebastien Bourdeauducqtravis/conda: build for python 3.5
2015-10-04 Sebastien Bourdeauducqtravis: activate py35
2015-10-04 Sebastien Bourdeauducqtravis: python 3.5
2015-09-30 Sebastien Bourdeauducqgenlib/fifo: add missing imports
2015-09-30 Sebastien Bourdeauducqtest/fifo: do not use Record
2015-09-30 Sebastien Bourdeauducqgenlib/fifo: remove Record support
2015-09-29 Sebastien Bourdeauducqbuild: stop at the first failed Quartus command
2015-09-29 Sebastien Bourdeauducqbuild: add missing import for Lattice Diamond
2015-09-29 Sebastien Bourdeauducqfhdl/FullMemoryWE: fix clocking
2015-09-29 Sebastien Bourdeauducqfhdl: typecheck ClockSignal and ResetSignal arguments
2015-09-28 Sebastien Bourdeauducqbuild: cleanup
2015-09-26 Sebastien Bourdeauducqfhdl/specials/Tristate: handle i=None
2015-09-26 Sebastien Bourdeauducqfhdl/structure: relax type requirements for Array elements
2015-09-26 Sebastien Bourdeauducqfhdl: replace flen with len
2015-09-26 Sebastien Bourdeauducqwrap expressions in Specials
2015-09-26 Sebastien Bourdeauducqfhdl: introduce wrap function
2015-09-26 Sebastien Bourdeauducqfhdl: export DUID
2015-09-24 Sebastien Bourdeauducqsetup: simpler version check, beta status
2015-09-23 Sebastien Bourdeauducqfsm: NextState and NextValue should derive from _Statement
2015-09-23 Sebastien Bourdeauducqsetup: remove unneeded import
2015-09-22 Sebastien BourdeauducqREADME.md->rst
2015-09-22 Sebastien Bourdeauducqsim: fix slice assign
2015-09-22 Sebastien Bourdeauducqconda: use new branch (revert this after merge)
2015-09-22 Sebastien Bourdeauducqsetup.py: cleanup
2015-09-22 Sebastien Bourdeauducqfsm: support complex targets in NextValue. Closes #27.
2015-09-22 Sebastien Bourdeauducqfhdl/namer: support ClockSignal and ResetSignal. Closes #24
2015-09-21 Sebastien Bourdeauducqsim: insert resets, support ClockSignal and ResetSignal
2015-09-21 Sebastien Bourdeauducqsim: drive clock signals
2015-09-21 Sebastien Bourdeauducqsim: VCD output support
2015-09-21 Sebastien Bourdeauducqverilog: remove unneeded import
2015-09-21 Sebastien Bourdeauducqdoc: minor edits
2015-09-20 Sebastien Bourdeauducqdoc: remove spurious file
2015-09-20 Sebastien Bourdeauducqdoc: remove outdated or moved parts, cleanup
2015-09-20 Sebastien Bourdeauducqfhdl/visit: support Constant
2015-09-20 Sebastien Bourdeauducqtravis: VPI is not there for now
2015-09-20 Sebastien Bourdeauducqsim: support generators yielding statements
2015-09-20 Sebastien Bourdeauducqsim: memory access from generators
2015-09-20 Sebastien Bourdeauducqfhdl/structure: add missing init
2015-09-19 Sebastien Bourdeauducqsim: memory support
2015-09-19 Sebastien Bourdeauducqfhdl/specials: MemoryPort.clock should always be a...
2015-09-19 Sebastien Bourdeauducqfhdl/simplify: add MemoryToArray
2015-09-19 Sebastien Bourdeauducqtest/fifo: convert to new API
2015-09-19 Sebastien Bourdeauducqgenlib/fifo: add missing import
2015-09-19 Sebastien Bourdeauducqsim: support arrays, and cat+slice in assignment target
2015-09-19 Florent Kermarrecmigen/genlib/cdc: fix BusSynchronizer
2015-09-19 Sebastien Bourdeauducqsim: remove unneeded import
2015-09-19 Sebastien Bourdeauducqgenlib/CRG: fix variable name conflict
2015-09-18 Sebastien Bourdeauducqtest: add divider
2015-09-17 Sebastien Bourdeauducqsim: support Case
2015-09-17 Sebastien Bourdeauducqsim: variables are deprecated
2015-09-17 Sebastien Bourdeauducqsim: fix comb evaluation
2015-09-17 Sebastien Bourdeauducqtest/size: do not test removed functions
2015-09-17 Sebastien Bourdeauducqtest/coding: use new API
2015-09-17 Sebastien Bourdeauducqgenlib/misc: add missing import
2015-09-17 Sebastien Bourdeauducqfhdl/structure: all case statements should be lists
2015-09-17 Sebastien Bourdeauducqfhdl/bitcontainer: remove fiter
2015-09-17 Sebastien Bourdeauducqminor bugfixes
2015-09-17 Sebastien Bourdeauducqsim: support eval of slice, cat and mux
2015-09-17 Sebastien Bourdeauducqfhdl/structure: fix namespace pollution
2015-09-17 Sebastien Bourdeauducqtest: bit reverse
2015-09-17 Sebastien Bourdeauducqfhdl/bitcontainer: remove fslice and freversed
2015-09-17 Sebastien Bourdeauducqtest/constant: use new API
2015-09-17 Robert Jordensadd unittests for Constant
2015-09-17 Sebastien Bourdeauducqdoc: Constant
2015-09-17 Sebastien Bourdeauducqfhdl/verilog: fix case value sort
2015-09-15 Sebastien Bourdeauducqfhdl/structure: introduce Constant, autowrap for eq...
2015-09-12 Sebastien Bourdeauducqfhdl/decorators: remove traces of deprecated API
2015-09-12 Sebastien Bourdeauducqgenlib: remove reverse_bytes, FlipFlop, Counter
2015-09-12 Sebastien Bourdeauducqgenlib: cleanup CRG
2015-09-12 Sebastien Bourdeauducqfhdl/decorators: remove deprecated API
2015-09-12 Sebastien Bourdeauducqsimplify imports, migen.fhdl.std -> migen
2015-09-12 Sebastien Bourdeauducqbuild/xilinx: minor cleanup
2015-09-12 Sebastien Bourdeauducqtest/support,signed,sort: use new simulator
2015-09-12 Sebastien Bourdeauducqsim: refactor comb commit
2015-09-12 Sebastien Bourdeauducqsim: support eval of nested lists
2015-09-12 Sebastien Bourdeauducqgenlib/sort: remove unneeded import
2015-09-12 Sebastien Bourdeauducqexamples/graycounter: use new simulator
2015-09-12 Sebastien Bourdeauducqtest/examples: do not attempt to run deleted examples
2015-09-12 Sebastien Bourdeauducqsim: support clock domains without sync
2015-09-11 Sebastien Bourdeauducqsimulator: support generators
2015-09-11 Sebastien Bourdeauducqnew simulator: basic execution
2015-09-11 Sebastien Bourdeauducqfhdl/tools: add input lister
2015-09-11 Sebastien Bourdeauducqstyle
2015-09-11 Sebastien Bourdeauducqfhdl: remove features new simulator won't use
2015-09-10 Sebastien Bourdeauducqremove genlib.misc.optree (use reduce instead)
2015-09-10 Yves Delleyfixed bug in value_bits_sign of mul operatiors
2015-09-10 Sebastien Bourdeauducqmibuild -> migen.build
2015-09-05 Sebastien BourdeauducqSimulator will be rewritten
2015-09-05 Sebastien BourdeauducqRemove code that will be into MiSoC or other packages.
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