yosys.git
2019-10-17 Miodrag MilanovicClean verilog code from not used define block
2019-10-17 Miodrag MilanovicRemoved alu and div_mod test as agreed, ignore generate...
2019-10-17 Miodrag MilanovicTest per flip-flop type
2019-10-17 Eddie HungAdd -assert
2019-10-17 Eddie HungUse built-in async2sync call as per #1417
2019-10-17 Eddie HungUpdate mul test to DSP48E1
2019-10-17 Eddie HungUpdate area for div_mod
2019-10-17 Eddie HungAdd comment for lack of tristate logic pointing to...
2019-10-17 Eddie HungMove $x to end as 7f0eec8
2019-10-17 SergeyDegtyaradffs test update (equiv_opt -multiclock)
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyDegtyarAdd comment with expected behavior for latches,tribuf...
2019-10-17 SergeyDegtyarFix latches.ys test
2019-10-17 SergeyDegtyarRemove xilinx_ug901 tests (will be moved to yosys-tests)
2019-10-17 SergeyDegtyarAdd smoke tests to tests/xilinx
2019-10-17 SergeyDegtyarAdd comments for unproven cells.
2019-10-17 SergeyDegtyarAdd tests for Xilinx UG901 examples
2019-10-16 Clifford WolfMerge pull request #1450 from YosysHQ/clifford/fixdffmux
2019-10-16 Clifford WolfFix dffmux peepopt init handling
2019-10-16 Clifford WolfMove GENERATE_PATTERN macro to separate utility header
2019-10-16 Pepijn de Vosremove duplicate DFFR
2019-10-16 Clifford WolfDisable left-over log_debug in peepopt_dffmux.pmg
2019-10-16 Clifford WolfFix parsing of .cname BLIF statements
2019-10-15 Clifford WolfAdd .blackbox support to blif front-end
2019-10-15 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-10-14 Clifford WolfMerge pull request #1448 from YosysHQ/daveshah1-sv...
2019-10-14 David ShahMerge pull request #1446 from YosysHQ/dave/ecp5-ioff
2019-10-14 Clifford WolfUse "(id)" instead of "id" for types as temporary hack
2019-10-11 David Shahecp5: Add ECLKBRIDGECS blackbox
2019-10-10 David Shahecp5: Add attrmvcp to copy syn_useioff to driving FF
2019-10-10 David Shahecp5: Set syn_useioff on IO FFs to enable packing
2019-10-10 Miodrag MilanovićMerge pull request #1445 from YosysHQ/mwk/xilinx_ibufg
2019-10-10 Marcin Kościelnickixilinx: Add simulation model for IBUFG.
2019-10-09 Benedikt TutzerFix renaming all classes to Cpp*
2019-10-09 Benedikt TutzerExpose global variables and allow logging to python...
2019-10-08 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 Eddie HungRevert "Add test that is expecting to fail"
2019-10-08 Eddie HungRevert "Be mindful that sigmap(wire) could have dupes...
2019-10-08 Eddie HungMerge pull request #1432 from YosysHQ/eddie/fix1427
2019-10-08 Eddie HungMerge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
2019-10-08 Eddie HungMerge pull request #1437 from YosysHQ/eddie/abc_to_abc9
2019-10-08 Eddie HungMerge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
2019-10-07 Eddie HungCleanup
2019-10-07 Eddie HungRename $currQ to $abc9_currQ
2019-10-07 Eddie HungUse "abc9_period" attribute for delay target
2019-10-07 Eddie HungGet rid of latch_* in write_xaiger
2019-10-07 Eddie HungUpdate comments in abc9_map.v
2019-10-07 Eddie HungRemove -D_ABC9
2019-10-07 Eddie HungRemove "write_xaiger -zinit"
2019-10-07 Eddie HungAdd comment on default flop init
2019-10-07 Eddie HungGet rid of output_port lookup
2019-10-06 Clifford WolfMerge pull request #1439 from YosysHQ/eddie/fix_ice40_w...
2019-10-06 Eddie HungDo not require changes to cells_sim.v; try and work...
2019-10-05 Eddie HungMissing 'accept' at end of ice40_wrapcarry, spotted...
2019-10-05 Clifford WolfUpdate README.md
2019-10-05 Eddie HungError if $currQ not found
2019-10-05 Eddie HungMissed this
2019-10-05 Eddie HungAdd comment on why we have to match for clock-enable...
2019-10-05 Eddie HungAdd note on pattern detector
2019-10-05 Miodrag MilanovićMerge pull request #1436 from YosysHQ/mmicko/msvc_fix
2019-10-05 Eddie HungAdd comment on why partial multipliers are 18x18
2019-10-05 Eddie HungAdd comments for xilinx_dsp_cascade
2019-10-05 Eddie HungImprove comments for xilinx_dsp_CREG
2019-10-05 Eddie HungFix comment
2019-10-05 Eddie HungRestore optimisation for sigM.empty()
2019-10-05 Eddie HungRetry on fixing TODOs
2019-10-05 Eddie HungRevert "Fix TODOs"
2019-10-05 Eddie HungMore comments, cleanup
2019-10-05 Eddie HungFix TODOs
2019-10-05 Eddie HungConsistency
2019-10-05 Eddie HungAdd comments for xilinx_dsp
2019-10-05 Eddie HungFix typo in check_label()
2019-10-05 Eddie Hungabc -> abc9
2019-10-05 Eddie HungMerge branch 'master' into eddie/abc_to_abc9
2019-10-05 Eddie HungFix from merge
2019-10-05 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-10-05 Eddie HungAdd temporary `abc9 -nomfs` and use for `synth_xilinx...
2019-10-05 Eddie HungUse read_args for read_verilog
2019-10-05 Eddie HungRemove DSP48E1 from *_cells_xtra.v
2019-10-05 Eddie HungFix merge issues
2019-10-04 Eddie HungMerge remote-tracking branch 'origin/eddie/abc_to_abc9...
2019-10-04 Eddie HungFix xilinx_dsp for unsigned extensions
2019-10-04 Eddie HungFix for SigSpec() == SigSpec(State::Sx, 0) to be true...
2019-10-04 Eddie HungAdd Const::{begin,end,empty}()
2019-10-04 Eddie HungRename abc_* names/attributes to more precisely be...
2019-10-04 Eddie HungPanic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 Eddie HungOops
2019-10-04 Eddie HungOhmilord this wasn't added all this time!?!
2019-10-04 Eddie HungAdd -async2sync to help text as per @daveshah1
2019-10-04 Miodrag MilanovicFixes for MSVC build
2019-10-04 Miodrag MilanovicFF should be initialized to 0
2019-10-04 Miodrag MilanovicSplit mux tests per type
2019-10-04 Miodrag MilanovicSplit latch check
2019-10-04 Miodrag MilanovicAdd missing latch mapping
2019-10-04 Miodrag Milanovicsplit rest od ff's
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