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yosys.git
2019-10-17
Miodrag Milanovic
Clean verilog code from not used define block
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2019-10-17
Miodrag Milanovic
Removed alu and div_mod test as agreed, ignore generate...
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2019-10-17
Miodrag Milanovic
Test per flip-flop type
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2019-10-17
Eddie Hung
Add -assert
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2019-10-17
Eddie Hung
Use built-in async2sync call as per #1417
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2019-10-17
Eddie Hung
Update mul test to DSP48E1
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2019-10-17
Eddie Hung
Update area for div_mod
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2019-10-17
Eddie Hung
Add comment for lack of tristate logic pointing to...
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2019-10-17
Eddie Hung
Move $x to end as 7f0eec8
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2019-10-17
SergeyDegtyar
adffs test update (equiv_opt -multiclock)
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
SergeyDegtyar
Add comment with expected behavior for latches,tribuf...
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2019-10-17
SergeyDegtyar
Fix latches.ys test
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2019-10-17
SergeyDegtyar
Remove xilinx_ug901 tests (will be moved to yosys-tests)
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2019-10-17
SergeyDegtyar
Add smoke tests to tests/xilinx
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2019-10-17
SergeyDegtyar
Add comments for unproven cells.
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2019-10-17
SergeyDegtyar
Add tests for Xilinx UG901 examples
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2019-10-16
Clifford Wolf
Merge pull request #1450 from YosysHQ/clifford/fixdffmux
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2019-10-16
Clifford Wolf
Fix dffmux peepopt init handling
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2019-10-16
Clifford Wolf
Move GENERATE_PATTERN macro to separate utility header
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2019-10-16
Pepijn de Vos
remove duplicate DFFR
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2019-10-16
Clifford Wolf
Disable left-over log_debug in peepopt_dffmux.pmg
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2019-10-16
Clifford Wolf
Fix parsing of .cname BLIF statements
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2019-10-15
Clifford Wolf
Add .blackbox support to blif front-end
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2019-10-15
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-10-14
Clifford Wolf
Merge pull request #1448 from YosysHQ/daveshah1-sv...
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2019-10-14
David Shah
Merge pull request #1446 from YosysHQ/dave/ecp5-ioff
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2019-10-14
Clifford Wolf
Use "(id)" instead of "id" for types as temporary hack
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2019-10-11
David Shah
ecp5: Add ECLKBRIDGECS blackbox
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2019-10-10
David Shah
ecp5: Add attrmvcp to copy syn_useioff to driving FF
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2019-10-10
David Shah
ecp5: Set syn_useioff on IO FFs to enable packing
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2019-10-10
Miodrag Milanović
Merge pull request #1445 from YosysHQ/mwk/xilinx_ibufg
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2019-10-10
Marcin Kościelnicki
xilinx: Add simulation model for IBUFG.
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2019-10-09
Benedikt Tutzer
Fix renaming all classes to Cpp*
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2019-10-09
Benedikt Tutzer
Expose global variables and allow logging to python...
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2019-10-08
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-08
Eddie Hung
Revert "Add test that is expecting to fail"
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2019-10-08
Eddie Hung
Revert "Be mindful that sigmap(wire) could have dupes...
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2019-10-08
Eddie Hung
Merge pull request #1432 from YosysHQ/eddie/fix1427
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2019-10-08
Eddie Hung
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
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2019-10-08
Eddie Hung
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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2019-10-08
Eddie Hung
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
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2019-10-07
Eddie Hung
Cleanup
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2019-10-07
Eddie Hung
Rename $currQ to $abc9_currQ
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2019-10-07
Eddie Hung
Use "abc9_period" attribute for delay target
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2019-10-07
Eddie Hung
Get rid of latch_* in write_xaiger
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2019-10-07
Eddie Hung
Update comments in abc9_map.v
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2019-10-07
Eddie Hung
Remove -D_ABC9
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2019-10-07
Eddie Hung
Remove "write_xaiger -zinit"
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2019-10-07
Eddie Hung
Add comment on default flop init
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2019-10-07
Eddie Hung
Get rid of output_port lookup
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2019-10-06
Clifford Wolf
Merge pull request #1439 from YosysHQ/eddie/fix_ice40_w...
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2019-10-06
Eddie Hung
Do not require changes to cells_sim.v; try and work...
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2019-10-05
Eddie Hung
Missing 'accept' at end of ice40_wrapcarry, spotted...
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2019-10-05
Clifford Wolf
Update README.md
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2019-10-05
Eddie Hung
Error if $currQ not found
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2019-10-05
Eddie Hung
Missed this
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2019-10-05
Eddie Hung
Add comment on why we have to match for clock-enable...
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2019-10-05
Eddie Hung
Add note on pattern detector
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2019-10-05
Miodrag Milanović
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix
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2019-10-05
Eddie Hung
Add comment on why partial multipliers are 18x18
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2019-10-05
Eddie Hung
Add comments for xilinx_dsp_cascade
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2019-10-05
Eddie Hung
Improve comments for xilinx_dsp_CREG
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2019-10-05
Eddie Hung
Fix comment
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2019-10-05
Eddie Hung
Restore optimisation for sigM.empty()
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2019-10-05
Eddie Hung
Retry on fixing TODOs
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2019-10-05
Eddie Hung
Revert "Fix TODOs"
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2019-10-05
Eddie Hung
More comments, cleanup
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2019-10-05
Eddie Hung
Fix TODOs
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2019-10-05
Eddie Hung
Consistency
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2019-10-05
Eddie Hung
Add comments for xilinx_dsp
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2019-10-05
Eddie Hung
Fix typo in check_label()
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2019-10-05
Eddie Hung
abc -> abc9
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2019-10-05
Eddie Hung
Merge branch 'master' into eddie/abc_to_abc9
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2019-10-05
Eddie Hung
Fix from merge
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2019-10-05
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-05
Eddie Hung
Add temporary `abc9 -nomfs` and use for `synth_xilinx...
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2019-10-05
Eddie Hung
Use read_args for read_verilog
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2019-10-05
Eddie Hung
Remove DSP48E1 from *_cells_xtra.v
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2019-10-05
Eddie Hung
Fix merge issues
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2019-10-04
Eddie Hung
Merge remote-tracking branch 'origin/eddie/abc_to_abc9...
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2019-10-04
Eddie Hung
Fix xilinx_dsp for unsigned extensions
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2019-10-04
Eddie Hung
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true...
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2019-10-04
Eddie Hung
Add Const::{begin,end,empty}()
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2019-10-04
Eddie Hung
Rename abc_* names/attributes to more precisely be...
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2019-10-04
Eddie Hung
Panic over. Model was elsewhere. Re-arrange for consistency
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2019-10-04
Eddie Hung
Oops
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2019-10-04
Eddie Hung
Ohmilord this wasn't added all this time!?!
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2019-10-04
Eddie Hung
Add -async2sync to help text as per @daveshah1
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2019-10-04
Miodrag Milanovic
Fixes for MSVC build
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2019-10-04
Miodrag Milanovic
FF should be initialized to 0
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2019-10-04
Miodrag Milanovic
Split mux tests per type
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2019-10-04
Miodrag Milanovic
Split latch check
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2019-10-04
Miodrag Milanovic
Add missing latch mapping
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2019-10-04
Miodrag Milanovic
split rest od ff's
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