yosys.git
2017-07-01 Clifford WolfFix and_or_buffer optimization in opt_expr for signed...
2017-07-01 Clifford WolfFix smtbmc vlogtb bug in $anyseq handling
2017-06-30 Clifford WolfAdd "design -import"
2017-06-30 Clifford WolfAdd chtype command
2017-06-30 Clifford WolfAdd $tribuf to opt_merge blacklist
2017-06-27 Clifford WolfMerge pull request #353 from azonenberg/master
2017-06-24 Andrew Zonenberggreenpak4_counters: Changed generation of primitive...
2017-06-20 Clifford WolfFix handling of init values in "abc -dff" and "abc...
2017-06-20 Clifford WolfFix history namespace collision
2017-06-20 Clifford WolfStore command history when terminating with an error
2017-06-20 Clifford WolfSwitched abc "clock domain not found" error to log_cmd_...
2017-06-07 Clifford WolfFix generation of vlogtb output in yosys-smtbmc for...
2017-06-01 Clifford WolfFix handling of Verilog ~& and ~| operators
2017-05-31 Clifford WolfUpdate ABC to hg rev efbf7f13ea9e
2017-05-31 Clifford WolfAdd dff2ff.v techmap file
2017-05-30 Clifford WolfFix AIGER back-end for multiple symbols per input/latch...
2017-05-28 Clifford WolfAdd "setundef -anyseq"
2017-05-28 Clifford WolfImprove write_aiger handling of unconnected nets and...
2017-05-27 Clifford WolfChange default smt2 solver to yices (Yices 2 has switch...
2017-05-24 Clifford WolfAdd aliases for common sets of gate types to "abc -g"
2017-05-23 Clifford WolfAdd examples/osu035
2017-05-23 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-05-23 Clifford WolfMerge pull request #346 from azonenberg/master
2017-05-23 Andrew Zonenberggreenpak4_counters: Added support for parallel output...
2017-05-17 Clifford WolfAdd workaround for CBMC bug to SimpleC back-end
2017-05-17 Clifford WolfEnable readline and tcl in mxe builds
2017-05-17 Clifford WolfAdd missing AndnotGate() and OrnotGate() declarations...
2017-05-17 Clifford WolfAdd $_ANDNOT_ and $_ORNOT_ gates
2017-05-16 Clifford WolfAdd <modname>_init() function generator to simpleC...
2017-05-16 Clifford WolfImprove simplec back-end
2017-05-15 Clifford WolfImprove simplec back-end
2017-05-14 Clifford WolfImprove simplec back-end
2017-05-13 Clifford WolfImprove simplec back-end
2017-05-12 Clifford WolfImprove simplec back-end
2017-05-12 Clifford WolfAdded support for more gate types to simplec back-end
2017-05-12 Clifford WolfAdd first draft of simple C back-end
2017-05-11 Clifford WolfUpdate ABC to hg rev e79576e10d72
2017-05-08 Clifford WolfFix boolector support in yosys-smtbmc
2017-04-30 Clifford WolfAdd support for localparam in module header
2017-04-28 Clifford WolfFix equiv_simple, old behavior now available with ...
2017-04-26 Clifford WolfAdd support for `resetall compiler directive
2017-04-12 Clifford WolfReplace CRLF line endings with LF in de2i.qsf (quartus...
2017-04-12 Larry DoolittleSquelch trailing whitespace
2017-04-07 Clifford WolfAdd MAX10 and Cyclone IV items to CHANGELOG
2017-04-07 Clifford WolfMerge pull request #337 from dh73/master
2017-04-06 dh73Add initial support for both MAX10 and Cyclone IV ...
2017-04-05 Clifford WolfAdd ConstEval defaultval feature
2017-04-05 Clifford WolfFix gcc compiler warning
2017-03-28 Clifford WolfAdd front-end detection for *.tcl files
2017-03-27 Clifford WolfAdd minisat 00_PATCH_typofixes.patch
2017-03-27 Clifford WolfRemove use of <fpu_control.h> in minisat
2017-03-20 Clifford WolfAdd "write_smt2 -stdt" mode
2017-03-19 Clifford WolfAdd generation of logic cells to EDIF back-end runtest.py
2017-03-19 Clifford WolfFix EDIF: portRef member 0 is always the MSB bit
2017-03-18 Clifford WolfAdd simple EDIF test case generator and checker
2017-03-14 Clifford WolfFix verilog pre-processor for multi-level relative...
2017-03-04 Clifford WolfImprove smt2 encodings of assert/assume/cover, better...
2017-03-02 Clifford WolfAdd write_aiger $anyseq support
2017-03-01 Clifford WolfAllow $anyconst, etc. in non-formal SV mode
2017-02-28 Clifford WolfDisable opt_merge for $anyseq and $anyconst
2017-02-28 Clifford WolfUse hex addresses in smtbmc vcd mem traces
2017-02-27 Clifford WolfAdd "chformal -assert2assume" and friends
2017-02-27 Clifford WolfAdd "chformal" pass
2017-02-26 Clifford WolfAdd smtbmc support for memory vcd dumping
2017-02-26 Clifford WolfFix extra newline bug in write_smt2
2017-02-26 Clifford WolfFix bug in smtio unroll code
2017-02-26 Clifford WolfFix assert checking in "yosys-smtbmc -c --append"
2017-02-26 Clifford WolfImprove (and fix for stbv mode) SMT2 memory API
2017-02-25 Clifford WolfAdd support for "yosys-smtbmc -c --append"
2017-02-25 Clifford WolfUpdate ABC to hg rev 3a95bfa55df7
2017-02-25 Clifford WolfMerge branch 'klammerj-master'
2017-02-25 Clifford WolfImprove "write_edif" help message
2017-02-25 Clifford WolfMove EdifNames out of double-private namespace
2017-02-25 Clifford WolfClean up edif code, swap bit indexing of "upto" ports
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair support to AIGER back-end.
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-24 Clifford WolfMerge pull request #322 from azonenberg/master
2017-02-24 Clifford WolfAdd "write_smt2 -stbv"
2017-02-24 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-24 Clifford WolfAdd SMT2 statebv mode (inactive for now)
2017-02-24 Johann KlammerDid as you requested, /but/...
2017-02-24 Clifford WolfMerge pull request #320 from joshhead/uninstall-binpath-fix
2017-02-24 Josh HeadapohlAdd missing slashes in paths for make uninstall
2017-02-23 Johann Klammeradd options for edif flavors
2017-02-23 Clifford WolfAdd support for SystemVerilog unique, unique0, and...
2017-02-23 Clifford WolfPreserve string parameters
2017-02-23 Clifford WolfFix mingw compile issue (2nd attempt)
2017-02-23 Clifford WolfFix mingw compile issue (maybe.. I can't test it)
2017-02-23 Clifford WolfAdded SystemVerilog support for ++ and --
2017-02-22 Clifford WolfUpdate ABC to hg rev 8da4dc435b9f
2017-02-19 Clifford WolfAdd "yosys-smtbmc -S <opt>"
2017-02-16 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-16 Clifford WolfCopy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 Clifford WolfFix eval implementation of $_NOR_
2017-02-14 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-14 Clifford WolfFix incorrect "incompatible re-declaration of wire...
2017-02-14 Clifford WolfAdd warning about x/z bits left unconnected in EDIF...
2017-02-14 Clifford WolfFix double-call of log_pop() in synth_greenpak4
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