yosys.git
2014-02-21 Clifford WolfAdded vhdl2verilog
2014-02-21 Clifford WolfProgress in presentation
2014-02-21 Clifford WolfBetter handling of nameDef and nameRef in edif backend
2014-02-21 Clifford WolfFixed instantiating multi-bit ports in edif backend
2014-02-21 Clifford WolfUse private namespace in mem_simple_4x1_map
2014-02-21 Clifford WolfAdded tests/techmap/mem_simple_4x1
2014-02-21 Clifford WolfRenamed "write_blif -subckt" to "write_blif -icells...
2014-02-21 Clifford WolfProgress in presentation
2014-02-20 Clifford WolfProgress in presentation
2014-02-20 Clifford WolfAdded _TECHMAP_REPLACE_ feature to techmap
2014-02-20 Clifford WolfAdded "extract -ignore_parameters" and "extract -ignore...
2014-02-20 Clifford WolfAdded "extract -map %<design_name>"
2014-02-20 Clifford WolfAdded "design -push" and "design -pop"
2014-02-20 Clifford WolfProgress in presentation
2014-02-20 Clifford WolfAdded connwrappers command
2014-02-20 Clifford WolfCleanups in handling of read_verilog -defer and -icells
2014-02-20 Clifford WolfProgress in presentation
2014-02-19 Clifford WolfAdded vcd2txt.pl and txt2tikztiming.py (tests/tools...
2014-02-18 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-18 Clifford WolfProgress in presentation
2014-02-18 Clifford WolfAdded techmap support for _TECHMAP_CONNMAP_*_
2014-02-18 Clifford WolfAdded "sat -dump_cnf"
2014-02-18 Clifford WolfCoding style corrections in SatHelper::dump_model_to_vcd()
2014-02-18 Clifford WolfImproved non-verbose ezSAT::printDIMACS() format
2014-02-18 Clifford WolfAdded "sat -initsteps"
2014-02-17 Clifford WolfAdded Verilog support for "`default_nettype none"
2014-02-17 Clifford WolfRenamed "sat -dump_fail_to_vcd" to "sat -dump_vcd"...
2014-02-17 Andrew ZonenbergAdded "-dump_fail_to_vcd" argument to SAT solver
2014-02-17 Clifford WolfProgress in presentation
2014-02-17 Clifford WolfBetter preserve wires when flattening (in comparison...
2014-02-16 Clifford WolfProgress in presentation
2014-02-16 Clifford WolfAdded some additional checks to techmap
2014-02-16 Clifford WolfAdded CONSTMSK and CONSTVAL feature to techmap
2014-02-16 Clifford WolfFixed handling of "keep" attribute on wires in opt_clean
2014-02-16 Clifford WolfAdded a warning note about error reporting to read_veri...
2014-02-16 Clifford WolfProgress in presentation
2014-02-16 Clifford WolfFixed use of selection in splitnets command
2014-02-16 Clifford WolfAdded recursion support to techmap
2014-02-16 Clifford WolfProgress in presentation
2014-02-16 Clifford WolfProgress in presentation
2014-02-16 Clifford WolfImproved support for constant functions
2014-02-15 Clifford WolfNow we are in Yoys 0.2.0+ development
2014-02-15 Clifford WolfTagging Yoys 0.2.0 yosys-0.2.0
2014-02-15 Clifford WolfAdded != support for relational select pattern
2014-02-15 Clifford WolfAdded iopadmap -bits
2014-02-15 Clifford WolfAdded ff and latch support to read_liberty
2014-02-15 Clifford WolfBugfix in expression parser of read_liberty
2014-02-15 Clifford WolfFixed dfflibmap for cell libraries with no set-reset-ff
2014-02-15 Clifford WolfCorrectly convert constants to RTLIL (fixed undef handling)
2014-02-15 Clifford WolfAdded frontend (-f) option to autotest.sh
2014-02-15 Clifford WolfFixed opt_const handling of double invert with non...
2014-02-15 Clifford WolfAdded liberty frontend
2014-02-14 Clifford WolfBe more conservative with new const-function code
2014-02-14 Clifford WolfAdded support for FOR loops in function calls in parameters
2014-02-14 Clifford WolfCreated basic support for function calls in parameter...
2014-02-14 Clifford WolfAdded abc -keepff option
2014-02-13 Clifford Wolfupdated default ABC command strings
2014-02-13 Clifford WolfUpdated ABC
2014-02-13 Clifford WolfImplemented read_verilog -defer
2014-02-13 Clifford WolfRemoved double blanks in ABC default command sequences
2014-02-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-13 Clifford WolfUpdated ABC and some related changes
2014-02-12 Clifford WolfMerge pull request #26 from ahmedirfan1983/btor
2014-02-12 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-12 Clifford WolfAdded support for functions returning integer
2014-02-12 Ahmed Irfanmodified btor synthesis script for correct use of splic...
2014-02-12 Clifford WolfDisabled "abc -dff" in "make test" for now (waiting...
2014-02-12 Clifford WolfUpdated ABC to rev e97a6e1d59b9
2014-02-11 Clifford Wolfrenamed ilang "scope error" to "ilang error"
2014-02-11 Ahmed Irfandisabling splice command in the script
2014-02-11 Ahmed Irfanregister output corrected
2014-02-11 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-02-11 Ahmed Irfanadded concat and slice cell translation
2014-02-11 Clifford WolfMore Makefile cleanups
2014-02-11 Clifford WolfImproved "make manual" and "make clean"
2014-02-09 Clifford WolfImproved ilang parser error messages
2014-02-09 Clifford Wolffixed a bug in subcircuit library with cells that have...
2014-02-09 Clifford WolfVarious improvements in expose command (added -sep...
2014-02-09 Clifford WolfAdded delete {-input|-output|-port}
2014-02-09 Clifford WolfBugfix in delete command
2014-02-08 Clifford WolfAdded test cases for expose -evert-dff
2014-02-08 Clifford WolfFixed handling of async reset in expose -evert-dff
2014-02-08 Clifford WolfBuild fixes for log cmd
2014-02-08 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-08 Clifford WolfImplemented expose -evert-dff
2014-02-08 Clifford WolfMerge pull request #24 from hansiglaser/master
2014-02-08 Johann Glaseradded "log" command
2014-02-08 Clifford WolfImproved checking of internal cell conventions
2014-02-08 Clifford WolfFixed bug in collecting of RD_TRANSPARENT parameter...
2014-02-08 Clifford WolfAdded various new options to splice command
2014-02-08 Clifford WolfAdded %a select operator
2014-02-08 Clifford WolfMoved some passes to other source directories
2014-02-08 Clifford WolfAdded support for "keep" attribute to abc pass
2014-02-08 Clifford WolfAdded opt -purge (frontend to opt_clean -purge)
2014-02-08 Clifford WolfOnly count non-trivial attributes when findinf master...
2014-02-08 Clifford WolfAdded checking for ABC modifications to Makefile and...
2014-02-07 Clifford WolfNow also move net labes to the right position in splice cmd
2014-02-07 Clifford WolfImproved detection of primary wire for a signal in...
2014-02-07 Clifford WolfAdded splice command
2014-02-07 Clifford WolfAdded log_header() to splitnets
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