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yosys.git
2014-09-29
Clifford Wolf
Added support for "keep" on modules
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Clifford Wolf
Merge pull request #39 from ahmedirfan1983/master
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-21
Clifford Wolf
Re-enabled assert for new logic loops in "share" pass
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2014-09-21
Clifford Wolf
Various improvements regarding logic loops in "share...
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2014-09-21
Clifford Wolf
Logic loop bugfix for "share" pass
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2014-09-21
Clifford Wolf
Added "share -limit"
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2014-09-21
Clifford Wolf
Still loop bug in "share": changed assert to warning
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2014-09-21
Clifford Wolf
Do not introduce new logic loops in "share"
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2014-09-21
Clifford Wolf
Assert on new logic loops in "share" pass
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2014-09-19
Clifford Wolf
Added "test_abcloop" command
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2014-09-19
Clifford Wolf
Initialize RTLIL::Const from std::vector<bool>
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2014-09-19
Clifford Wolf
Sorting of object names in ilang backend
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2014-09-19
Clifford Wolf
Small improvements in "abc" command handle_loops()...
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2014-09-19
Clifford Wolf
Using "NOT" instead of "INV" as cell name in default...
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2014-09-19
Clifford Wolf
Alphabetically sort port names in "show" output
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2014-09-18
Clifford Wolf
Do not run "scorr" in "abc -fast"
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2014-09-18
Clifford Wolf
Improvements in "synth" script
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2014-09-18
Clifford Wolf
Added "abc -fast"
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2014-09-18
ahmedirfan1983
fixed memory next issue, when same memory is written...
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2014-09-17
Clifford Wolf
Added commit count to devel version number
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2014-09-16
Clifford Wolf
Fixed $_NOR vs. $_NOR_ typo in abc.cc
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2014-09-16
Clifford Wolf
Fixed $memwr/$memrd order in memory_dff
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2014-09-16
Clifford Wolf
Added new CodingReadme file (replaces CodingStyle and...
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2014-09-16
Clifford Wolf
Fixed $macc simlib model for zero-config
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2014-09-15
Clifford Wolf
More aggressive $macc merging in alumacc
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2014-09-15
Clifford Wolf
Added the obvious optimizations to alumacc $macc generator
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2014-09-15
Clifford Wolf
Improved maccmap tree bit packing
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2014-09-15
Clifford Wolf
Fixed wreduce $shiftx handling
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2014-09-14
Clifford Wolf
Fixed monitor notifications for removed cell
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2014-09-14
Clifford Wolf
Added "synth" command
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2014-09-14
Clifford Wolf
Fixed techmap_wrap for techmap_celltype
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2014-09-14
Clifford Wolf
Using alumacc in techmap.v
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2014-09-14
Clifford Wolf
Various fixes/cleanups in alumacc and maccmap
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2014-09-14
Clifford Wolf
Added techmap_wrap attribute
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2014-09-14
Clifford Wolf
alumacc fix for $pos cells
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2014-09-14
Clifford Wolf
Extract $alu cells in alumacc
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2014-09-14
Clifford Wolf
Merge $macc cells in alumacc pass
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2014-09-14
Clifford Wolf
Basic $macc extract in alumacc
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2014-09-14
Clifford Wolf
alumacc skeleton
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2014-09-14
Clifford Wolf
Cleanup in wreduce
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2014-09-13
Clifford Wolf
Using pkg-config to find libffi
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2014-09-08
Clifford Wolf
Fixed simlib $macc model for xilinx xsim
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2014-09-08
Clifford Wolf
Simplified $fa undef model
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2014-09-08
Clifford Wolf
Fixes and cleanups for blackbox.v
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2014-09-08
Clifford Wolf
Added $lcu cell type
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2014-09-08
Clifford Wolf
Another $clog2 bugfix
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2014-09-08
Clifford Wolf
Added "$fa" cell type
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2014-09-08
Clifford Wolf
Trim msb/lsb zero bits from full adder in maccmap
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2014-09-08
Clifford Wolf
Added "test_cell -const"
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2014-09-07
Clifford Wolf
Using maccmap for $macc and $mul techmap
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2014-09-07
Clifford Wolf
Added 'techmap_maccmap' techmap attribute
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2014-09-07
Clifford Wolf
Added "maccmap" command
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2014-09-07
Clifford Wolf
Added "test_cell -nosat"
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2014-09-06
Clifford Wolf
Various bug fixes (related to $macc model testing)
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2014-09-06
Clifford Wolf
Added $macc eval model
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2014-09-06
Clifford Wolf
Added $macc SAT model
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2014-09-06
Clifford Wolf
Fixed $clog2 (off by one error)
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2014-09-06
Clifford Wolf
Added $macc simlib model (also use as techmap rule...
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2014-09-06
Clifford Wolf
Fixed assignment of out-of bounds array element
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2014-09-06
Clifford Wolf
Added $macc cell type
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2014-09-06
Clifford Wolf
Fixed autotest for non-basename arguments
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2014-09-06
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-09-06
Clifford Wolf
Added "test_cell -script"
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2014-09-06
Clifford Wolf
Merge pull request #38 from rubund/master
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2014-09-06
Ruben Undheim
Corrected spelling mistakes found by lintian
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2014-09-04
Clifford Wolf
Added tests/various/constmsk_test.ys
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2014-09-04
Clifford Wolf
Fixed "opt_const -fine" for $pos cells
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2014-09-04
Clifford Wolf
Removed $bu0 cell type
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2014-09-03
Clifford Wolf
Using $pos models for $bu0
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2014-09-03
Clifford Wolf
Fixed "test_cells -vlog"
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2014-09-03
Clifford Wolf
Fixes in $alu SAT- and eval-models
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2014-09-02
Clifford Wolf
Undef-related fixes in simlib $alu model
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2014-09-02
Clifford Wolf
Improvements in "test_cell -vlog"
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2014-09-02
Clifford Wolf
Added test_cell -vlog
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2014-09-02
Clifford Wolf
Create a default selection stack in RTLIL::Design:...
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2014-09-02
Clifford Wolf
Small bug fixes in $not, $neg, and $shiftx models
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2014-09-02
Clifford Wolf
Added SAT testing to test_cell eval stage
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2014-09-02
Ahmed Irfan
added $pmux cell translation
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2014-09-02
Clifford Wolf
Removed references to yosys-svgviewer from docs
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2014-09-02
Clifford Wolf
Removed yosys-svgviewer
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2014-09-02
Clifford Wolf
Using "xdot" instead of "yosys-svgviewer" in show command
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2014-09-01
Clifford Wolf
Added $alu support to test_cell
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2014-09-01
Clifford Wolf
Added ConstEval model for $alu cells
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2014-09-01
Clifford Wolf
Added SAT model for $alu cells
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2014-09-01
Clifford Wolf
Fixed "test_cell -simlib all"
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2014-09-01
Clifford Wolf
Added "test_cell -simlib -v"
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2014-09-01
Clifford Wolf
Added "techmap -autoproc"
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2014-09-01
Clifford Wolf
Fixes in old SAT example.ys
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2014-09-01
Clifford Wolf
Moved "share" and "wreduce" to passes/opt/
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2014-09-01
Clifford Wolf
Using std::vector<RTLIL::State> instead of RTLIL::Const...
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2014-08-31
Clifford Wolf
Added eval testing to test_cell
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2014-08-31
Clifford Wolf
Fixed return size of const_*() eval functions
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2014-08-31
Clifford Wolf
Added RTLIL::Const::size()
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2014-08-31
Clifford Wolf
Added eval model for $lut cells
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2014-08-31
Clifford Wolf
Typo fixes in cell->*Param() API
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2014-08-31
Clifford Wolf
Added $lut support in test_cell, techmap, satgen
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2014-08-30
Clifford Wolf
Added design->scratchpad
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2014-08-30
Clifford Wolf
Added $alu cell type
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