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gem5.git
2014-06-01
Steve Reinhardt
style: eliminate equality tests with true and false
stable_2014_08_26
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2014-05-25
Nilay Vaish
stats: changes due to recent o3 patch.
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2014-05-23
Nilay Vaish
stats: changes due to o3 cpu and ruby message buffer...
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2014-05-23
Nilay Vaish
ruby: slicc: remove unused ids DNUCA*
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2014-05-23
Nilay Vaish
ruby: remove old protocol documentation
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2014-05-23
Nilay Vaish
ruby: message buffer: drop dequeue_getDelayCycles()
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2014-05-23
Nilay Vaish
cpu: o3: remove stat totalCommittedInsts
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2014-05-15
Anthony Gutierrez
config: remove unecessary assignment of etherlink inter...
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2014-05-12
Steve Reinhardt
syscall emulation: clean up & comment SyscallReturn
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2014-05-12
Steve Reinhardt
tests: update t1000 & pc-switcheroo-full stats
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2014-05-11
Steve Reinhardt
tests: update eio ref outputs for new stats
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2014-05-09
Andreas Hansson
stats: Bump stats for the fixes, and mostly DRAM contro...
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2014-05-09
Andreas Hansson
config: Bump DRAM sweep bus speed to match DDR4 config
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2014-05-09
Andreas Hansson
tests: Reflect name change in DRAM tests
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2014-05-09
Andreas Hansson
mem: Update DDR3 and DDR4 based on datasheets
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2014-05-09
Andreas Hansson
mem: Add DRAM cycle time
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2014-05-09
Andreas Hansson
mem: Simplify DRAM response scheduling
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2014-05-09
Andreas Hansson
mem: Add precharge all (PREA) to the DRAM controller
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2014-05-09
Andreas Hansson
mem: Remove printing of DRAM params
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2014-05-09
Andreas Hansson
mem: Add tRTP to the DRAM controller
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2014-05-09
Andreas Hansson
mem: Merge DRAM latency calculation and bank state...
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2014-05-09
Andreas Hansson
mem: Add tWR to DRAM activate and precharge constraints
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2014-05-09
Andreas Hansson
mem: Merge DRAM page-management calculations
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2014-05-09
Andreas Hansson
mem: Add DRAM power states to the controller
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2014-05-09
Andreas Hansson
mem: Ensure DRAM refresh respects timings
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2014-05-09
Andreas Hansson
mem: Make DRAM read/write switching less conservative
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2014-04-17
Ali Saidi
arm: Make sure UndefinedInstructions are properly initi...
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2014-04-17
Ali Saidi
arm: allow DC instructions by default so SE mode works
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2014-04-17
Ali Saidi
sim, arm: implement more of the at variety syscalls
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2014-05-09
Andrew Bardsley
cpu: Useful getters for ActivityRecorder
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2014-05-09
Andrew Bardsley
cpu: Add flag name printing to StaticInst
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2014-05-09
Andrew Bardsley
cpu: Timebuf const accessors
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2014-05-09
Andrew Bardsley
arm: Add branch flags onto macroops
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2014-05-09
Andrew Bardsley
cpu: Allow setWhen on trace objects
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2014-05-09
Curtis Dunham
arm: add preliminary ISA splits for ARM arch
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2014-05-09
Curtis Dunham
arch: teach ISA parser how to split code across files
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2014-05-09
Geoffrey Blake
config: Avoid generating a reference to myself for...
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2014-05-09
Geoffrey Blake
arch, arm: Preserve TLB bootUncacheability when switchi...
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2014-05-09
Curtis Dunham
cpu: add more instruction mix statistics
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2014-05-09
Mitch Hayenga
mem: Squash prefetch requests from downstream caches
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2014-05-09
Stephan Diestelhorst
stats: Method stats source
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2014-05-09
Akash Bagdia
cpu, arm: Allow the specification of a socket field
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2014-05-09
Sascha Bischoff
mem: Auto-generate CommMonitor trace file names
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2014-05-09
Geoffrey Blake
arm: Panics in miscreg read functions can be tripped...
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2014-05-09
Chris Emmons
dev: Set HDLCD default pixel clock for 1080p @ 60Hz
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2014-05-09
Matt Evans
arm: quick hack to allow a greater number of CPUs to...
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2014-05-09
Eric Van Hensbergen
arm: Add Makefile for aarch64 build of util/m5
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2014-05-09
Curtis Dunham
arch: remove inline specifiers on all inst constrs...
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2014-05-09
Curtis Dunham
arm: cleanup ARM ISA definition
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2014-03-20
Curtis Dunham
ext: disable PLY debugging
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2014-05-09
Curtis Dunham
scons: Require SWIG >= 2.0.4 and remove vector typemaps
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2014-04-23
Curtis Dunham
arm: Correctly display disassembly of vldmia/vstmia
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2014-04-23
Mitch Hayenga
util: Valgrind suppression addition
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2014-04-23
Andreas Hansson
sim: Use correct unit for abort message
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2014-04-23
Mitchell Hayenga
cpu: Fix setTranslateLatency() bug for squashed instruc...
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2014-04-23
Sascha Bischoff
misc: Proper type check and import for PortRef
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2014-04-01
Mitch Hayenga
cpu: Fix case where o3 lsq could print out uninitialize...
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2014-04-01
Mitch Hayenga
mem: Don't print out the data of a cache block
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2014-04-23
Mitchell Hayenga
arm: Don't use a stack allocated mnemonic
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2014-04-23
Dam Sunwoo
cpu: Add O3 CPU width checks
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2014-04-23
Curtis Dunham
base: explicitly suggest potential use of 'All' debug...
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2014-04-23
Curtis Dunham
arch: remove 'null update' check in isa-parser
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2014-02-11
Curtis Dunham
stats: better error message for uninitialized statistic
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2014-04-22
Andreas Hansson
stats: updates for pc-switcheroo-full due to o3 smt fix
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2014-04-19
Nilay Vaish
stats: updates due to o3 smt fix
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2014-04-19
Nilay Vaish
ruby: slicc: remove old documentation
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2014-04-19
Nilay Vaish
ruby: slicc: slight change to rule for transitions
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2014-04-19
Faissal Sleiman
o3: Fix occupancy checks for SMT
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2014-04-19
Marco Elver
ruby: recorder: Fix (de-)serializing with different...
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2014-04-19
Nilay Vaish
config: ruby: remove memory controller from network...
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2014-04-14
Anthony Gutierrez
arm: set default kernels for VExpress_EMM and VExpress_...
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2014-04-13
Andreas Hansson
scons: Fix python-config parsing by adding strip()
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2014-04-10
Gedare Bloom
config: add num-work-ids command line option
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2014-04-10
Stian Hvatum
scons: compile on systems where python2 and python3...
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2014-04-09
Andreas Sandberg
kvm, x86: Add initial support for multicore simulation
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2014-04-09
Andreas Sandberg
dev: Protect PollEvent processing when running in paral...
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2014-04-08
Nilay Vaish
ruby: slicc: change enqueue statement
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2014-04-08
Nilay Vaish
ruby: coherence protocols: drop the phrase IntraChip
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2014-04-03
Andreas Sandberg
sim: Add the ability to lock and migrate between event...
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2014-04-01
Anthony Gutierrez
ext: add McPAT source
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2014-04-01
Anthony Gutierrez
arm: fix typos in makefile for ARM m5 util and link...
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2014-04-01
Nilay Vaish
configs: use SimpleMemory when using ruby in se mode
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2014-03-25
Marco Elver
cpu: o3: lsq: Fix TSO implementation
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2014-03-23
Andreas Hansson
stats: Update stats for DRAM changes
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2014-03-23
Andreas Hansson
mem: Track DRAM read/write switching and add hysteresis
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2014-03-23
Andreas Hansson
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
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2014-03-23
Andreas Hansson
mem: Change memory defaults to be more representative
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2014-03-23
Wendy Elsasser
mem: Add close adaptive paging policy to DRAM controlle...
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2014-03-23
Andreas Hansson
mem: DRAM controller tidying up
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2014-03-23
Andreas Hansson
mem: Fix bug in DRAM bytes per activate
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2014-03-23
Andreas Hansson
mem: Limit the accesses to a page before forcing a...
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2014-03-23
Andreas Hansson
mem: Make DRAM write queue draining more aggressive
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2014-03-23
Andreas Hansson
config: Add a DRAM efficiency-sweep script
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2014-03-23
Neha Agarwal
cpu: DRAM Traffic Generator
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2014-03-23
Neha Agarwal
mem: DDR3 config for comparing with DRAMSim2
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2014-03-23
Andreas Hansson
mem: More descriptive address-mapping scheme names
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2014-03-23
Curtis Dunham
scons: Shush scons
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2014-03-23
Stan Czerniawski
misc: Fix -q (quiet) flag
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2014-03-23
Andreas Hansson
ruby: Move Ruby debug flags to ruby dir and remove...
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2014-03-23
Andreas Hansson
util: Add support for detection of gzipped packet traces
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