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microwatt.git
2019-09-12
Anton Blanchard
Merge pull request #49 from antonblanchard/icache-2
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2019-09-12
Anton Blanchard
Add a simple direct mapped icache
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2019-09-12
Anton Blanchard
SOC memory wishbone should clear ACK regardless of STB
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2019-09-12
Anton Blanchard
Merge pull request #48 from antonblanchard/clk_gen_bypass
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2019-09-12
Anton Blanchard
Fix clk_gen_bypass
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2019-09-11
Anton Blanchard
Merge pull request #47 from antonblanchard/if-fix
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2019-09-11
Anton Blanchard
Merge pull request #46 from antonblanchard/record-fix
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2019-09-11
Anton Blanchard
Explicitly check against '1' in if statements
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2019-09-11
Anton Blanchard
Remove names from end record statements
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2019-09-11
Anton Blanchard
Merge pull request #45 from antonblanchard/fixes
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2019-09-11
Anton Blanchard
Fix issue in loadstore1
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2019-09-11
Anton Blanchard
Fix issue in execute2
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2019-09-11
Anton Blanchard
Merge pull request #44 from antonblanchard/nia-remove
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2019-09-11
Anton Blanchard
Remove nia from loadstore and multiply
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2019-09-11
Anton Blanchard
Merge pull request #43 from mikey/trivial
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2019-09-11
Michael Neuling
Remove FIXME comment
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2019-09-11
Anton Blanchard
Merge pull request #41 from mikey/travis
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2019-09-11
Anton Blanchard
Merge pull request #42 from antonblanchard/fetch-rework-v2
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2019-09-11
Anton Blanchard
Reformat core.vhdl
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2019-09-11
Anton Blanchard
Remove sim console
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2019-09-11
Anton Blanchard
Reduce multiply to 2 cycles
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2019-09-11
Anton Blanchard
Register outputs on writeback
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2019-09-11
Anton Blanchard
Register outputs on execute2
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2019-09-11
Anton Blanchard
Register outputs on loadstore1
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2019-09-11
Anton Blanchard
Move debug execute output into decode2
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2019-09-11
Anton Blanchard
Rework pipeline, add stall and flush signals
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2019-09-11
Michael Neuling
Allow a full make check on Travis
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2019-09-10
Anton Blanchard
Merge pull request #40 from antonblanchard/makefile...
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2019-09-10
Anton Blanchard
Update Makefile dependencies
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2019-09-10
Benjamin Herrenschmidt
Switch soc to use std_ulogic
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2019-09-10
Benjamin Herrenschmidt
Share soc.vhdl between FPGA and sim
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2019-09-10
Benjamin Herrenschmidt
Pass wishbone record to bram memory module
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2019-09-10
Benjamin Herrenschmidt
Rework wishbone slave address decoding
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2019-09-10
Benjamin Herrenschmidt
Move wishbone arbiter out of the core
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2019-09-10
Benjamin Herrenschmidt
Re-indent and reformat soc.vhdl
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2019-09-10
Benjamin Herrenschmidt
Split FPGA toplevel from soc
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2019-09-10
Anton Blanchard
Merge pull request #39 from antonblanchard/no-x-state
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2019-09-10
Anton Blanchard
Don't send out X state from the memory behavioural
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2019-09-10
Anton Blanchard
Merge pull request #36 from mikey/gitignore
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2019-09-10
Anton Blanchard
Merge pull request #38 from antonblanchard/multiply...
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2019-09-10
Anton Blanchard
Quieten multiply warning
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2019-09-10
Michael Neuling
Add new files to git ignore
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2019-09-09
Anton Blanchard
Merge pull request #35 from antonblanchard/multiply-opt
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2019-09-09
Anton Blanchard
Simplify multiply
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2019-09-09
Anton Blanchard
Merge pull request #34 from antonblanchard/decode-table
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2019-09-09
Anton Blanchard
Add a decode bit to mark an instruction as single throu...
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2019-09-09
Benjamin Herrenschmidt
decode1 array fix header
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2019-09-09
Anton Blanchard
Merge pull request #33 from antonblanchard/cr-fix
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2019-09-09
Anton Blanchard
Merge pull request #32 from antonblanchard/register...
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2019-09-09
Benjamin Herrenschmidt
Use simulated UART in core test bench
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2019-09-09
Benjamin Herrenschmidt
Make sim poll non-blocking
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2019-09-09
Benjamin Herrenschmidt
Add simulated UART design
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2019-09-09
Anton Blanchard
Fix CR forwarding
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2019-09-09
Anton Blanchard
Add forwarding in the register file
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2019-09-09
Anton Blanchard
Merge pull request #31 from antonblanchard/no-second...
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2019-09-09
Anton Blanchard
Merge pull request #30 from antonblanchard/writeback...
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2019-09-09
Anton Blanchard
More second write port removal
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2019-09-09
Anton Blanchard
Add some assertions to writeback
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2019-09-09
Anton Blanchard
Merge pull request #29 from antonblanchard/no-second...
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2019-09-09
Anton Blanchard
Merge pull request #28 from antonblanchard/loadstore...
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2019-09-09
Anton Blanchard
Remove second write port
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2019-09-09
Anton Blanchard
Remove some more loadstore debug
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2019-09-09
Anton Blanchard
Merge pull request #27 from antonblanchard/fix-cr
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2019-09-09
Anton Blanchard
Fix issues with CR rework
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2019-09-09
Anton Blanchard
Merge pull request #26 from antonblanchard/silence...
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2019-09-09
Anton Blanchard
Merge pull request #25 from antonblanchard/register_fil...
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2019-09-09
Anton Blanchard
Merge pull request #24 from antonblanchard/cr_file_cleanup
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2019-09-09
Anton Blanchard
Silence some loadstore related debug
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2019-09-09
Anton Blanchard
Clean up register read debug output
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2019-09-09
Anton Blanchard
Rework CR file and add forwarding
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2019-09-08
Anton Blanchard
Merge pull request #19 from antonblanchard/cmod-a7
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2019-09-08
Anton Blanchard
Cmod A7-35 support
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2019-09-08
Anton Blanchard
Merge pull request #20 from antonblanchard/reset-rework2
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2019-09-08
Anton Blanchard
Merge pull request #22 from antonblanchard/store-fix
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2019-09-08
Anton Blanchard
Stores need to wait for wishbone write ack
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2019-09-08
Anton Blanchard
Merge pull request #21 from antonblanchard/xdc-update
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2019-09-07
Anton Blanchard
Add CONFIG_VOLTAGE and CFGBVS entries
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2019-09-07
Anton Blanchard
Rework SOC reset
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2019-09-07
Anton Blanchard
Rename a few reset signals
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2019-09-06
Anton Blanchard
Merge pull request #18 from mikey/verific
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2019-09-06
Michael Neuling
Fix verific script with new VHDL files
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2019-09-06
Anton Blanchard
Merge pull request #17 from antonblanchard/writeback...
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2019-09-05
Anton Blanchard
Use a better input signal in writeback
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2019-09-03
Anton Blanchard
Merge pull request #16 from antonblanchard/decode2_rework2
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2019-09-03
Anton Blanchard
Rework decode2
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2019-08-31
Anton Blanchard
Merge pull request #13 from mikey/dynamic-ranges
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2019-08-30
Michael Neuling
Remove dynamic ranges from code
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2019-08-29
Anton Blanchard
Merge pull request #10 from antonblanchard/arty-fix
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2019-08-29
Anton Blanchard
Arty A7 reset pin is C2
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2019-08-29
Anton Blanchard
Merge pull request #7 from riktw/fusesoc_arty_a7
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2019-08-29
Anton Blanchard
Merge pull request #9 from antonblanchard/travis-fix
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2019-08-29
Anton Blanchard
A few Travis CI fixes
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2019-08-29
riktw
Added support for building for Arty A7 boards
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2019-08-28
Anton Blanchard
Merge pull request #5 from antonblanchard/travis-test
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2019-08-28
Anton Blanchard
Add an initial travis.yml
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2019-08-28
Anton Blanchard
Add srd and srw
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2019-08-28
Anton Blanchard
Add sim only divw
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2019-08-27
Anton Blanchard
Fix ghdl build error with pp_soc_memory
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2019-08-27
Anton Blanchard
micropython only requires 512kB of BRAM
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2019-08-27
Anton Blanchard
Merge pull request #6 from mikey/gif
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