yosys.git
2020-03-13 Alberto GonzalezAdd support for optimizing exists-forall problems.
2020-03-06 Miodrag MilanovićMerge pull request #1742 from nakengelhardt/rpc-test...
2020-03-06 N. Engelhardtrpc test: make frontend listen before launching yosys...
2020-03-05 Eddie HungMerge pull request #1739 from YosysHQ/eddie/issue1738
2020-03-05 Eddie Hungice40: fix specify for ICE40_{LP,U}
2020-03-05 Eddie Hungtests: extend tests/arch/run-tests.sh for defines
2020-03-04 Eddie Hungice40: fix implicit signal in specify, also clamp negat...
2020-03-04 Eddie HungMerge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1
2020-03-04 Eddie Hungxilinx: consider DSP48E1.ADREG
2020-03-04 Eddie Hungxilinx: cleanup DSP48E1 handling for abc9
2020-03-04 Eddie Hungxilinx: improve specify for DSP48E1
2020-03-04 Eddie Hungxilinx: missing DSP48E1.PCIN timing from abc9_{map...
2020-03-03 N. EngelhardtMerge pull request #1691 from ZirconiumX/use-flowmap...
2020-03-03 Claire WolfFix bison warning for "pure-parser" option
2020-03-03 Claire WolfMerge pull request #1718 from boqwxp/precise_locations
2020-03-03 Claire WolfMerge pull request #1681 from YosysHQ/eddie/fix1663
2020-03-03 Claire WolfMerge pull request #1519 from YosysHQ/eddie/submod_po
2020-03-02 Marcelina Kościelnickaiopadmap: Look harder for already-present buffers....
2020-03-02 Eddie HungMerge pull request #1724 from YosysHQ/eddie/abc9_specify
2020-03-02 N. EngelhardtMerge pull request #1729 from rqou/coolrunner2
2020-03-02 R. Oucoolrunner2: Attempt to give wires/cells more meaningfu...
2020-03-02 R. Oucoolrunner2: Fix invalid multiple fanouts of XOR/OR...
2020-03-02 R. Oucoolrunner2: Fix packed register+input buffer insertion
2020-03-02 R. Oucoolrunner2: Insert many more required feedthrough...
2020-02-29 Eddie HungMerge pull request #1727 from YosysHQ/eddie/fix_write_smt2
2020-02-28 Eddie Hungystests: fix write_smt2_write_smt2_cyclic_dependency_fail
2020-02-28 Eddie HungMerge pull request #1726 from YosysHQ/eddie/fix1710
2020-02-28 Dan RavensloftAdd -flowmap to synth and synth_ice40
2020-02-28 Eddie Hungast: fixes #1710; do not generate RTLIL for unreachable...
2020-02-28 Eddie HungComment out log()
2020-02-27 Eddie HungRemove RAMB{18,36}E1 from cells_xtra.py
2020-02-27 Eddie HungSmall fixes
2020-02-27 Eddie HungFixes for older compilers
2020-02-27 Eddie HungRevert "Fix tests/arch/xilinx/fsm.ys to count flops...
2020-02-27 Eddie Hungast: quiet down when deriving blackbox modules
2020-02-27 Eddie Hungabc9_ops: suppress -prep_box warning for abc9_flop
2020-02-27 Eddie Hungxilinx: Update RAMB* specify entries
2020-02-27 Eddie Hungice40: add delays to SB_CARRY
2020-02-27 Eddie Hungxilinx: add delays to INV
2020-02-27 Eddie HungMake TimingInfo::TimingInfo(SigBit) constructor explicit
2020-02-27 Eddie HungTimingInfo: index by (port_name,offset)
2020-02-27 Eddie HungFix spacing
2020-02-27 Eddie HungMore +/ice40/cells_sim.v fixes
2020-02-27 Eddie HungCleanup tests
2020-02-27 Eddie HungUpdate bug1630.ys to use -lut 4 instead of lut file
2020-02-27 Eddie HungMake +/xilinx/cells_sim.v legal
2020-02-27 Eddie Hungabc9_ops: still emit delay table even box has no timing
2020-02-27 Eddie Hungwrite_xaiger: add comment about arrival times of flop...
2020-02-27 Eddie Hungabc9_ops: demote lack of box timing info to warning
2020-02-27 Eddie HungGet rid of (* abc9_{arrival,required} *) entirely
2020-02-27 Eddie Hungabc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 Eddie Hungabc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 Eddie Hungabc9_ops: add and use new TimingInfo struct
2020-02-27 Eddie HungFix tests/arch/xilinx/fsm.ys to count flops only
2020-02-27 Eddie HungExpand +/xilinx/cells_sim.v to keep ICARUS and non...
2020-02-27 Eddie Hungice40: fix specify for inverted clocks
2020-02-27 Eddie HungFix tests by gating some specify constructs from iverilog
2020-02-27 Eddie HungUpdate simple_abc9 tests
2020-02-27 Eddie Hungabc9_ops: ignore (* abc9_flop *) if not '-dff'
2020-02-27 Eddie Hungice40: specify fixes
2020-02-27 Eddie Hungabc9_ops: sort LUT delays to be ascending
2020-02-27 Eddie Hungice40: move over to specify blocks for -abc9
2020-02-27 Eddie Hungsynth_ecp5: use +/abc9_model.v
2020-02-27 Eddie HungUpdate xilinx for ABC9
2020-02-27 Eddie HungCreate +/abc9_model.v for $__ABC9_{DELAY,FF_}
2020-02-27 Eddie Hungabc9_ops: output LUT area
2020-02-27 Eddie Hungecp5: remove small LUT entries
2020-02-27 Eddie Hungabc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto...
2020-02-27 Eddie HungFix commented out specify statement
2020-02-27 Eddie Hungxilinx: improve specify functionality
2020-02-27 Eddie Hungecp5: deprecate abc9_{arrival,required} and *.{lut...
2020-02-27 Eddie Hungxilinx: use specify blocks in place of abc9_{arrival...
2020-02-27 Eddie HungAuto-generate .box/.lut files from specify blocks
2020-02-27 Eddie Hungabc9_ops: assert on $specify2 properties
2020-02-27 Eddie Hungabc9_ops: -prep_box, to be called once
2020-02-27 Eddie Hungabc9_ops: -prep_lut and -write_lut to auto-generate...
2020-02-27 Claire WolfMerge pull request #1709 from rqou/coolrunner2_counter
2020-02-27 Claire WolfMerge pull request #1708 from rqou/coolrunner2-buf-fix
2020-02-27 Piotr Binkowskixilinx: mark IOBUFDSE3 IOB pin as external
2020-02-26 Miodrag MilanovićMerge pull request #1705 from YosysHQ/logger_pass
2020-02-26 Miodrag MilanovicRemove tests for now
2020-02-24 Alberto GonzalezChange attribute search value to specify precise locati...
2020-02-24 Alberto GonzalezChange attribute search value to specify precise locati...
2020-02-23 Miodrag MilanovicAdd tests for logger pass
2020-02-23 Miodrag MilanovicRemove duplicate warning detection
2020-02-23 Miodrag MilanovicFix line endings
2020-02-23 Alberto GonzalezCloses #1717. Add more precise Verilog source location...
2020-02-22 Eddie HungMerge pull request #1715 from boqwxp/master
2020-02-22 Miodrag MilanovicUpdate explanation for expect-no-warnings
2020-02-22 Miodrag MilanovicHandle expect no warnings together with expected
2020-02-22 Miodrag MilanovicCheck other regex parameters
2020-02-22 Alberto GonzalezCloses #1714. Fix make failure when NDEBUG=1.
2020-02-21 Eddie HungMerge pull request #1703 from YosysHQ/eddie/specify_improve
2020-02-20 Claire WolfMerge pull request #1642 from jjj11x/jjj11x/sv-enum
2020-02-20 Miodrag Milanoviccheck for regex errors
2020-02-19 Eddie Hungverilog: add support for more delays than just rise...
2020-02-19 Eddie Hungclean: ignore specify-s inside cells when determining...
2020-02-17 Miodrag MilanovicPrevent double error message
2020-02-17 Miodrag MilanovicOption to expect no warnings
2020-02-17 Miodrag MilanovicAdd to changelog
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