2018-09-07 |
Florent Kermarrec | soc_sdram: revert vivado l2 cache workaround (still... |
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2018-09-07 |
Florent Kermarrec | targets: pass endianness to LiteEThMAC, tftp working... |
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2018-09-06 |
Jean-François... | libnet/microudp: (WIP) fix endianness issues |
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2018-09-06 |
enjoy-digital | Merge pull request #98 from jfng/fix_typo |
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2018-09-06 |
Jean-François... | fix typo and unused include |
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2018-09-06 |
Florent Kermarrec | cpu/minerva: add workaround on import until code is... |
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2018-09-06 |
Florent Kermarrec | setup.py: create litex_sim exec to ease simulation |
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2018-09-05 |
Jean-François... | add Minerva support |
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2018-09-05 |
Florent Kermarrec | litex_server: update pcie and remove bar_size parameter |
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2018-09-04 |
Tim Ansell | Merge pull request #96 from cr1901/tinyfpga_bx |
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2018-09-04 |
William D.... | build/platforms: Add TinyFPGA BX board and programmer. |
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2018-09-04 |
Tim Ansell | Merge pull request #95 from cr1901/lm32-lite |
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2018-09-03 |
William D.... | Add lm32 "lite" variant, remove mult/div from "minimal... |
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2018-08-31 |
Florent Kermarrec | README: update |
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2018-08-28 |
enjoy-digital | Merge pull request #94 from cr1901/nextpnr |
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2018-08-28 |
William D.... | lattice/icestorm: Add nextpnr pnr as alternate pnr... |
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2018-08-24 |
Tim Ansell | Merge pull request #93 from phlipped/master |
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2018-08-24 |
phlipped | Fix URL for liteUSB |
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2018-08-23 |
Tim Ansell | Merge pull request #91 from cr1901/ignore-fix |
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2018-08-23 |
Tim Ansell | Merge pull request #92 from cr1901/l2-gate |
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2018-08-23 |
William D.... | .gitignore: litex/build contains valid source, so exclu... |
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2018-08-23 |
William D.... | software/bios: Gate flush_l2_cache() if L2 Cache isn... |
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2018-08-22 |
Florent Kermarrec | bios/sdram: improve/simplify read window selection |
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2018-08-22 |
Florent Kermarrec | sim: run as root only when needed (ethernet module... |
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2018-08-22 |
Florent Kermarrec | builder: change call to get_sdram_phy_c_header and... |
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2018-08-22 |
Florent Kermarrec | soc_sdram: cosmetic |
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2018-08-22 |
Florent Kermarrec | soc_sdram: vivado is now able to implement the l2_cache... |
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2018-08-21 |
Florent Kermarrec | soc_core: add cpu_endianness |
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2018-08-21 |
Florent Kermarrec | builder: get_sdram_phy_header renamed to get_sdram_phy_... |
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2018-08-21 |
Florent Kermarrec | soc_sdram: use new LiteDRAMWishbone2Native and port... |
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2018-08-21 |
Florent Kermarrec | vexriscv: update |
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2018-08-20 |
Florent Kermarrec | soc/integration: move sdram_init to litedram |
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2018-08-18 |
Florent Kermarrec | Vexriscv: update csr-defs.h |
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2018-08-18 |
Florent Kermarrec | update Vexriscv |
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2018-08-18 |
Florent Kermarrec | bios/sdram: changes to ease manual read window selection |
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2018-08-17 |
Florent Kermarrec | litex_server: allow multiple clients to connect to... |
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2018-08-17 |
Florent Kermarrec | cpu/lm32: add minimal variant with no i/d cache, pipeli... |
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2018-08-16 |
Florent Kermarrec | bios/boot: flush all caches before running from ram |
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2018-08-16 |
Florent Kermarrec | sim/verilator: catch ctrl-c on exit and revert default... |
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2018-08-16 |
Florent Kermarrec | cpu_interace: use riscv64-unknown-elf if available... |
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2018-08-14 |
Florent Kermarrec | bios/sdram: fix read_level_scan result |
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2018-08-12 |
enjoy-digital | Merge pull request #86 from pgielda/patch-1 |
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2018-08-12 |
Peter Gielda | Fix generating csr.csv file |
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2018-08-08 |
Florent Kermarrec | soc/intergration/cpu_interface: typo |
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2018-08-07 |
Florent Kermarrec | bios/main: use edata instead of erodata |
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2018-08-07 |
Florent Kermarrec | picorv32: add reset signal |
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2018-08-06 |
Florent Kermarrec | soc/software/bios: add reboot command |
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2018-08-06 |
Florent Kermarrec | soc/integration/soc_core: add Controller with reset... |
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2018-08-06 |
Florent Kermarrec | soc/interconnect/wishbone: add Timeout to avoid stallin... |
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2018-08-06 |
Florent Kermarrec | soc/cores/cpu: add reset signal |
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2018-07-27 |
enjoy-digital | Merge pull request #81 from xobs/vexriscv-to-wishbone |
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2018-07-27 |
Sean Cross | tools: remove vexriscv_debug |
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2018-07-27 |
Sean Cross | vexriscv: reset wishbone bus on CPU reset |
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2018-07-27 |
Sean Cross | vexriscv: put debug bus directly on wishbone bus |
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2018-07-20 |
Florent Kermarrec | add litex_setup script to clone and install Migen,... |
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2018-07-20 |
Florent Kermarrec | build/generic_platform: use list for sources instead... |
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2018-07-19 |
Florent Kermarrec | bios/sdram: add ERR_DDRPH_BITSLIP constant and some... |
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2018-07-19 |
Florent Kermarrec | soc/integration/soc_sdram: add assertion on csr_data_wi... |
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2018-07-19 |
Florent Kermarrec | setup.pu: fix exclude |
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2018-07-18 |
Florent Kermarrec | boards/plarforms/genesys2: replace user_dip_sw with... |
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2018-07-18 |
Florent Kermarrec | boards/platforms/genesys2: add minimum HPC connectors... |
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2018-07-18 |
Florent Kermarrec | setup.py: exclude test, sim, doc directories |
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2018-07-18 |
Florent Kermarrec | software/bios/linker: revert data section since require... |
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2018-07-17 |
enjoy-digital | Merge pull request #80 from xobs/fix-vexriscv-csr-read |
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2018-07-17 |
Sean Cross | vexriscv_debug: use csr read()/write() accessors |
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2018-07-16 |
Florent Kermarrec | soc/integration/sdram_init: use fixed burst_length... |
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2018-07-16 |
Florent Kermarrec | targets/nexys_video: remove read leveling constants... |
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2018-07-16 |
Florent Kermarrec | targets/nexys4ddr: s7ddrphy now supports ddr2, working |
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2018-07-16 |
Florent Kermarrec | bios/sdram: improve bitslip selection when window can... |
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2018-07-10 |
Florent Kermarrec | soc/cores/uart: rename UARTMultiplexer to RS232PHYMulti... |
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2018-07-10 |
Florent Kermarrec | soc_core: add csr_expose parameter to be able to expose... |
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2018-07-06 |
Florent Kermarrec | bios/sdram: improve read leveling (artix7 read-leveling... |
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2018-07-06 |
Florent Kermarrec | bios/sdram: fix compilation with no write leveling |
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2018-07-06 |
enjoy-digital | Merge pull request #79 from xobs/fix-vexriscv-data... |
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2018-07-06 |
Sean Cross | vexriscv: debug: fix reading DATA register |
commit | commitdiff | tree |
2018-07-06 |
enjoy-digital | Merge pull request #78 from xobs/vexriscv_debug_bridge |
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2018-07-06 |
Sean Cross | setup: add vexriscv_debug to list of entrypoints |
commit | commitdiff | tree |
2018-07-06 |
Sean Cross | tools: vexriscv_debug: add debug bridge |
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2018-07-05 |
Florent Kermarrec | cores/cpu/vexriscv: create variants: None and "debug... |
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2018-07-05 |
Florent Kermarrec | core/cpu/vexriscv/core: improve indentation |
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2018-07-05 |
enjoy-digital | Merge pull request #77 from xobs/debug-vexriscv-enjoy |
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2018-07-05 |
Florent Kermarrec | platforms/arty_s7: keep up to date with Migen |
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2018-07-05 |
Sean Cross | soc_core: uart: add a reset line to the UART |
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2018-07-05 |
Sean Cross | soc: integration: use the new cpu_debugging flag for... |
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2018-07-05 |
Sean Cross | soc: vexriscv: add cpu debug support |
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2018-07-05 |
Sean Cross | vexriscv: verilog: pull debug-enabled verilog |
commit | commitdiff | tree |
2018-07-05 |
Florent Kermarrec | platforms/arty: merge with Migen |
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2018-07-05 |
Florent Kermarrec | platforms/kc705: keep up to date with Migen |
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2018-07-05 |
Florent Kermarrec | platforms/de0nano: keep up to date with Migen |
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2018-07-05 |
Florent Kermarrec | README/boards: add precision on Migen's platforms |
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2018-07-02 |
Florent Kermarrec | bios/sdram: also check for last read of scan to choose... |
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2018-07-02 |
Florent Kermarrec | bios/main: add cpu frequency to banner |
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2018-07-02 |
Florent Kermarrec | bios/sdram: check for optimal read window before doing... |
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2018-06-29 |
Florent Kermarrec | soc/cores/code_8b10b: update (from misoc) |
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2018-06-28 |
Florent Kermarrec | bios/sdram: use new phy, improve scan, allow disabling... |
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2018-06-28 |
Florent Kermarrec | software/bios: fix picorv32 boot_helper |
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2018-06-27 |
Florent Kermarrec | bios/sdram: add write/read leveling scans |
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2018-06-27 |
Florent Kermarrec | boards: add genesys2 (platform with clk/serial/dram... |
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2018-06-19 |
Florent Kermarrec | soc_core: remove assert on interrupt (added to catch... |
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2018-06-18 |
Florent Kermarrec | soc/integration/cpu_interface: add shadow_base parameter |
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