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yosys.git
2019-04-20
Eddie Hung
Merge remote-tracking branch 'origin' into xc7srl
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2019-04-20
Clifford Wolf
Merge pull request #942 from YosysHQ/clifford/fix931
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2019-04-19
Clifford Wolf
Improve "show" handling of 0/1/X/Z padding
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2019-04-19
Clifford Wolf
Change "ne" to "neq" in btor2 output
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2019-04-19
Clifford Wolf
Add tests/aiger/.gitignore
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2019-04-19
Eddie Hung
Spelling fixes
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2019-04-18
Clifford Wolf
Update to ABC 3709744
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2019-04-18
Eddie Hung
Merge pull request #917 from YosysHQ/eddie/fix_retime
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2019-04-18
Eddie Hung
Fix abc's remap_name to not ignore [^0-9] when extracti...
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2019-04-18
Eddie Hung
ABC to call retime all the time
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2019-04-18
Eddie Hung
Revert "synth_* with -retime option now calls abc with...
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2019-04-18
Eddie Hung
Merge branch 'master' into eddie/fix_retime
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2019-04-18
Clifford Wolf
Improve proc full_case detection and handling, fixes...
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2019-04-17
Clifford Wolf
Update to ABC d1b6413
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2019-04-16
Eddie Hung
Merge pull request #939 from YosysHQ/revert895
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2019-04-16
Eddie Hung
Revert #895
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2019-04-16
Eddie Hung
Merge pull request #937 from YosysHQ/revert-932-eddie...
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2019-04-16
Eddie Hung
Revert "Recognise default entry in case even if all...
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2019-04-15
Eddie Hung
Merge pull request #936 from YosysHQ/README-fix-quotes
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2019-04-15
whitequark
README: fix some incorrect quoting.
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2019-04-12
Eddie Hung
Merge pull request #928 from litghost/add_xc7_sim_models
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2019-04-12
Keith Rothman
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
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2019-04-12
Clifford Wolf
Merge pull request #933 from dh73/master
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2019-04-12
Clifford Wolf
Merge pull request #932 from YosysHQ/eddie/fixdlatch
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2019-04-12
Diego
Fixing issues in CycloneV cell sim
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2019-04-11
Eddie Hung
Add default entry to testcase
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2019-04-11
Eddie Hung
Recognise default entry in case even if all cases cover...
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2019-04-10
Eddie Hung
synth_* with -retime option now calls abc with -D 1...
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2019-04-10
Eddie Hung
Revert "abc -dff now implies "-D 0" otherwise retiming...
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2019-04-10
Eddie Hung
Revert ""&nf -D 0" fails => use "-D 1" instead"
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2019-04-10
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-04-09
Keith Rothman
Fix LUT6_2 definition.
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2019-04-09
Keith Rothman
Add additional cells sim models for core 7-series prima...
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2019-04-08
Eddie Hung
Fix a few typos
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2019-04-08
Eddie Hung
$_XILINX_SHREG_ to preserve src attribute
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2019-04-08
Eddie Hung
Update CHANGELOG
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2019-04-08
Eddie Hung
Merge branch 'undo_pr895' into xc7srl
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2019-04-08
Eddie Hung
Undo #895 by instead setting an attribute
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2019-04-08
Eddie Hung
Cope with undoing #895
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2019-04-08
Clifford Wolf
Merge pull request #919 from YosysHQ/multiport_transp
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2019-04-08
Eddie Hung
Revert "Remove handling for $pmux, since #895"
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2019-04-07
David Shah
memory_bram: Fix multiport make_transp
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2019-04-06
Eddie Hung
Call shregmap twice -- once for variable, another for...
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2019-04-05
Eddie Hung
Merge branch 'eddie/fix_retime' into xc7srl
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2019-04-05
Eddie Hung
Add retime test
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2019-04-05
Eddie Hung
Fix S0 -> S1
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2019-04-05
Eddie Hung
Move dffinit til after abc
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2019-04-05
Eddie Hung
Merge branch 'eddie/fix_retime' into xc7srl
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2019-04-05
Eddie Hung
Move techamp t:$_DFF_?N? to before abc call
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2019-04-05
Eddie Hung
Retry
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2019-04-05
Eddie Hung
"&nf -D 0" fails => use "-D 1" instead
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2019-04-05
Eddie Hung
Resolve @daveshah1 comment, update synth_xilinx help
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2019-04-05
Eddie Hung
synth_xilinx to techmap FFs after abc call, otherwise...
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2019-04-05
Eddie Hung
abc -dff now implies "-D 0" otherwise retiming doesn...
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2019-04-05
Eddie Hung
techmap inside map_cells stage
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2019-04-05
Clifford Wolf
Add "read_ilang -lib"
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2019-04-04
Clifford Wolf
Added missing argument checking to "mutate" command
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2019-04-04
Eddie Hung
Merge branch 'map_cells_before_map_luts' into xc7srl
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2019-04-04
Eddie Hung
Missing techmap entry in help
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2019-04-04
Eddie Hung
Use soft-logic, not LUT3 instantiation
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2019-04-04
Eddie Hung
Merge branch 'map_cells_before_map_luts' into xc7srl
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2019-04-04
Eddie Hung
synth_xilinx to map_cells before map_luts
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2019-04-04
Eddie Hung
Cleanup comments
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2019-04-04
Eddie Hung
t:$dff* -> t:$dff t:$dffe
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2019-04-03
Eddie Hung
Remove handling for $pmux, since #895
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2019-04-03
Eddie Hung
-nosrl meant when -nobram
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2019-04-03
Eddie Hung
Remove duplicate STARTUPE2
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2019-04-03
Eddie Hung
Disable shregmap in synth_xilinx if -retime
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2019-04-03
Eddie Hung
Add changelog entry
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2019-04-03
Eddie Hung
Merge pull request #913 from smunaut/fix_proc_mux
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2019-04-03
Sylvain Munaut
proc_mux: Fix crash when trying to optimize non-existan...
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2019-04-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-03
Clifford Wolf
Merge pull request #912 from YosysHQ/bram_addr_en
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2019-04-03
Clifford Wolf
Merge pull request #910 from ucb-bar/memupdates
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2019-04-02
David Shah
memory_bram: Consider read enable for address expansion...
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2019-04-02
Eddie Hung
Merge pull request #895 from YosysHQ/pmux2shiftx
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2019-04-01
Jim Lawson
Refine memory support to deal with general Verilog...
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2019-03-29
Clifford Wolf
Merge pull request #907 from YosysHQ/clifford/fix906
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2019-03-29
Clifford Wolf
Build Verilog parser with -DYYMAXDEPTH=100000, fixes...
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2019-03-28
Clifford Wolf
Merge pull request #901 from trcwm/libertyfixes
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2019-03-28
Clifford Wolf
Merge pull request #903 from YosysHQ/bram_reset_transp
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2019-03-27
David Shah
memory_bram: Reset make_transp when growing read ports
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Clifford Wolf
Add "read -verific" and "read -noverific"
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2019-03-27
Clifford Wolf
Add "rename -output"
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2019-03-27
Clifford Wolf
Improve "rename" help message
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2019-03-26
Clifford Wolf
Add "cutpoint -undef"
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2019-03-26
Clifford Wolf
Add "hdlname" attribute
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2019-03-26
Clifford Wolf
Fix "verific -extnets" for more complex situations
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2019-03-25
Eddie Hung
synth_xilinx to use shregmap with -minlen 3
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2019-03-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-25
Clifford Wolf
Add "cutpoint" pass
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2019-03-25
Eddie Hung
Create one $shiftx per bit in width
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2019-03-25
Clifford Wolf
Merge pull request #896 from YosysHQ/transp_fixes
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2019-03-25
Clifford Wolf
Merge pull request #897 from trcwm/libertyfixes
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2019-03-25
Niels Moseley
spaces -> tabs
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2019-03-25
Niels Moseley
EOL is now accepted as ';' replacement on lines that...
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2019-03-24
Niels Moseley
Updated the liberty parser to accept [A:B] ranges ...
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