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gem5.git
2012-02-29
Steve Reinhardt
EIO: update stats (mostly order change, some renames)
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2012-02-26
Gabe Black
Make the IO bridge accept address headed to all the...
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2012-02-26
Gabe Black
X86: Use the M5PanicFault fault in execute methods...
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2012-02-24
Andreas Hansson
MEM: Simplify cache ports preparing for master/slave...
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2012-02-24
Andreas Hansson
MEM: Prepare mport for master/slave split
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2012-02-24
Andreas Hansson
Ruby: Simplify tester ports by not using SimpleTimingPort
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2012-02-24
Andreas Hansson
MEM: Move all read/write blob functions from Port to...
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2012-02-24
Andreas Hansson
MEM: Make port proxies use references rather than pointers
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2012-02-24
Andreas Hansson
MEM: Move port creation to the memory object(s) constru...
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2012-02-24
Andreas Hansson
CPU: Round-two unifying instr/data CPU ports across...
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2012-02-24
Andreas Hansson
MEM: Fatal when no port can be found for an address
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2012-02-20
Steve Reinhardt
SimObject: make get_config_as_dict() tolerate undefined...
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2012-02-14
Andreas Hansson
MEM: Fix residual bus ports and make them master/slave
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2012-02-14
Andreas Hansson
Script: Fix the scripts that use the num_cpus cache...
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2012-02-14
Andreas Hansson
MEM: Fix master/slave ports in Ruby and non-regression...
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2012-02-13
Ali Saidi
bp: fix up stats for changes to branch predictor
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2012-02-13
Mrinmoy Ghosh
BPred: Fix RAS to handle predicated call/return instruc...
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2012-02-13
Mrinmoy Ghosh
BP: Fix several Branch Predictor issues.
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2012-02-13
Andreas Hansson
MEM: Explicit ports and Python binding on CopyEngine
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2012-02-13
Andreas Hansson
MEM: Pass the ports from Python to C++ using the Swig...
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2012-02-13
Andreas Hansson
MEM: Introduce the master/slave port roles in the Pytho...
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2012-02-13
Ali Saidi
tests: fix diff-out script for op/inst stat changes.
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2012-02-13
Gabe Black
X86: open flags: Another patch from Vince Weaver
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2012-02-12
Ali Saidi
configs: fix minor config bugs posted on the mailing...
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2012-02-12
Ali Saidi
stats: update stats for insts/ops and master id changes
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2012-02-12
Anthony Gutierrez
cpu: add separate stats for insts/ops both globally...
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2012-02-12
Dam Sunwoo
mem: fix cache stats to use request ids correctly
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2012-02-12
Ali Saidi
mem: Add a master ID to each request object.
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2012-02-12
Mrinmoy Ghosh
prefetcher: Make prefetcher a sim object instead of...
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2012-02-12
Nilay Vaish
Regressions: Update stats due to change in MESI protocol
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2012-02-11
Gabe Black
SPARC: Make PSTATE and HPSTATE a BitUnion.
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2012-02-10
Nilay Vaish
Ruby: Remove isTagPresent() calls from Sequencer.cc
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2012-02-10
Nilay Vaish
MESI: Add queues for stalled requests
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2012-02-10
Nilay Vaish
sim/system: initialize the pagePtr variable
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2012-02-10
Nilay Vaish
Regressions: Update stats due to O3 CPU changes
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2012-02-10
Nilay Vaish
O3 CPU: Improve handling of delayed commit flag
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2012-02-10
Nilay Vaish
O3 CPU: Strengthen condition for handling interrupts
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2012-02-10
Nilay Vaish
O3 CPU: Provide the squashing instruction
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2012-02-10
Nilay Vaish
O3 Fetch: Check if PC is pointing to Microcode ROM
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2012-02-10
Gabe Black
SE/FS: Record the system pointer all the time for the...
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2012-02-09
Andreas Hansson
MEM: Remove onRetryList from BusPort and rely on retryList
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2012-02-07
Gabe Black
Checker: Access workload element 0 only if there is...
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2012-02-07
Gabe Black
Faults: Turn off arch/faults.hh
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2012-02-07
Gabe Black
m5=>gem5: Make the regression script build gem5.* inste...
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2012-02-05
Gabe Black
X86: Rename the bridge which allows commnication back...
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2012-02-05
Gabe Black
Regressions: Fix the regress script when "all" is used.
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2012-02-03
Gabe Black
System: Forgot to qrefresh with my last change.
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2012-02-03
Gabe Black
System: Fix the check which detects running out of...
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2012-02-02
Andreas Hansson
Regression: Update the regress script after SE/FS merge
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2012-02-01
Ali Saidi
configs: More fixes for the memory system updates
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2012-02-01
Gabe Black
Merge ... head, hopefully the last time for this batch.
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2012-01-31
Koan-Sin Tan
clang: Enable compiling gem5 using clang 2.9 and 3.0
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2012-01-31
Andreas Hansson
MEM: Remove the otherPort from the cache ports
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2012-01-31
Andreas Hansson
Thread: Use inherited baseCpu rather than cpu in Simple...
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2012-01-31
Dam Sunwoo
util: implements "writefile" gem5 op to export file...
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2012-01-31
Geoffrey Blake
CheckerCPU: Re-factor CheckerCPU to be compatible with...
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2012-01-31
Gabe Black
Merge with main repository.
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2012-01-30
Andreas Hansson
Ruby: Connect system port in Ruby network test
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2012-01-30
Andreas Hansson
MEM: Make the RubyPort physMemPort a PioPort instead...
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2012-01-30
Andreas Hansson
MEM: Clean-up of Functional/Virtual/TranslatingPort...
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2012-01-29
Gabe Black
Yet another merge with the main repository.
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2012-01-29
Gabe Black
Implement Ali's review feedback.
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2012-01-29
Nilay Vaish
Config: Enable O3 CPU and Ruby in FS mode
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2012-01-29
Nilay Vaish
X86 Regressions: Update stats due to introduction of TSO
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2012-01-29
Nilay Vaish
O3 CPU LSQ: Implement TSO
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2012-01-28
Gabe Black
SE/FS: Get rid of the FULL_SYSTEM config option.
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2012-01-28
Gabe Black
SE/FS: Pull FULL_SYSTEM out of the build_opts files
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2012-01-28
Gabe Black
SE/FS: Get rid of FULL_SYSTEM in the configs directory
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2012-01-28
Gabe Black
SE/FS: Make both SE and FS tests available all the...
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2012-01-28
Gabe Black
SE/FS: Make SE vs. FS mode a runtime parameter.
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2012-01-28
Gabe Black
MIPS: Fix a compiler warning from the eret instruction.
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2012-01-28
Gabe Black
Merge with the main repo.
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2012-01-27
Andreas Hansson
ns_gige: Fix a missing curly brace in if-statement
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2012-01-26
Ronald Dreslinski
configs: actually add ARMv7a-like cpu/cache file
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2012-01-26
Ronald Dreslinski
configs: A more realistic configuration of an ARM-like...
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2012-01-25
Andreas Hansson
MEM: Fix fs.py by specifying the range size rather...
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2012-01-16
Gabe Black
Merge yet again with the main repository.
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2012-01-12
Mitchell Hayenga
Fix memory corruption issue with CopyStringOut()
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2012-01-25
Ali Saidi
stats: Update stats for final tick and memory bandwidth...
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2012-01-25
Ali Saidi
sim: display final value of curTick in stats
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2012-01-25
Ali Saidi
Mem: Add simple bandwidth stats to PhysicalMemory
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2012-01-23
Nilay Vaish
Config: Enable using O3 CPU and Ruby in SE mode
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2012-01-23
Nilay Vaish
O3, Ruby: Forward invalidations from Ruby to O3 CPU
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2012-01-23
Nilay Vaish
MemCmd: Add a command for invalidation requests to LSQ
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2012-01-17
Andreas Hansson
MEM: Make the bus default port yet another port
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2012-01-17
Andreas Hansson
MEM: Removing the default port peer from Python ports
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2012-01-17
Andreas Hansson
MEM: Make the bus bridge unidirectional and fixed addre...
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2012-01-17
William Wang
MEM: Remove the functional ports from the memory system
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2012-01-17
Andreas Hansson
MEM: Separate queries for snooping and address ranges
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2012-01-17
Andreas Hansson
MEM: Remove Port removeConn and MemObject deletePortRefs
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2012-01-17
Andreas Hansson
MEM: Remove the notion of the default port
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2012-01-17
Andreas Hansson
MEM: Simplify ports by removing EventManager
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2012-01-17
Andreas Hansson
CPU: Moving towards a more general port across CPU...
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2012-01-17
Andreas Hansson
MEM: Add port proxies instead of non-structural ports
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2012-01-17
Andreas Hansson
Ruby: Change the access permissions for MOESI hammer
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2012-01-17
Andreas Hansson
Ruby: Change the access permissions for MOESI hammer
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2012-01-17
Andreas Hansson
MEM: Add the system port as a central access point
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2012-01-17
Andreas Hansson
MEM: Differentiate functional cache accesses from CPU...
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2012-01-17
Ali Saidi
stats: undo parser change from initparam change
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2012-01-17
Steve Reinhardt
Alpha: warn_once about broken PAL breakpoints.
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