riscv-isa-sim.git
2016-09-10 Andrew Watermanallow MAFDC bits in MISA to be modified
2016-09-06 Tim NewsomeRemove generic debug tests. (#65)
2016-09-02 Andrew WatermanMerge pull request #62 from riscv/trigger
2016-09-02 Tim NewsomeMerge branch 'master' into trigger
2016-09-02 Tim NewsomeRebuild debug ROM because CSR encoding changed.
2016-09-02 Tim NewsomeSupport triggers on TLB misses.
2016-09-01 Tim NewsomeTheoretically support trigger timing.
2016-08-31 Tim NewsomeRename tdata[0-2] to tdata[1-3].
2016-08-31 Tim NewsomeSave/restore tselect. Set dmode.
2016-08-29 Tim NewsomeFix indent.
2016-08-29 Tim NewsomeRename tdata0--tdata2 to tdata1--tdata3.
2016-08-27 Andrew WatermanAdd (degenerate) performance counter facility
2016-08-26 Andrew WatermanAllow reads from tdrdata registers
2016-08-26 Andrew Watermanpartially update spike to newer debug spec
2016-08-26 Andrew WatermanFix spike interactive (-d) mode
2016-08-23 Andrew Watermanremove HWBPCOUNT field of DCSR
2016-08-22 Tim NewsomeImplement address and data triggers.
2016-08-17 Andrew WatermanAllow mstatus.MPP to store bad values; instead, validat...
2016-08-16 Colin Schmidtremove old rvc directory (#61)
2016-07-28 Tim NewsomeAdd support for virtual priv register. (#59)
2016-07-22 Andrew WatermanSet U bit in misa register
2016-07-19 Tim NewsomeMake address translation work in 32-bit. (#58)
2016-07-13 Tim NewsomeFix single step over csrw instructions. (#57)
2016-07-12 Andrew WatermanDon't treat RVC NOP as illegal instruction
2016-07-12 Andrew WatermanFix page table walker not respecting valid bit
2016-07-06 Andrew WatermanUpdate to new PTE format
2016-07-01 Tim NewsomeRemove debug printf that was cluttering up output.
2016-06-29 Andrew WatermanDisassemble RVC instructions based on XLEN
2016-06-28 Tim NewsomeMake gdbserver code work with small Debug RAM.
2016-06-28 Tim NewsomeSupport debugging 32-bit spike instances.
2016-06-23 Andrew WatermanParameterize debug ROM contents on XLEN
2016-06-23 Andrew WatermanRemove fence.i from debug ROM
2016-06-23 Andrew WatermanDon't use I$ in debug mode
2016-06-23 Andrew WatermanRemove legacy HTIF; implement HTIF directly
2016-06-23 Andrew WatermanFix paddr_bits computation prior to VM setup
2016-06-18 Andrew WatermanMerge sasid into sptbr
2016-06-09 Andrew WatermanTrap on tdrdata registers when tdrselect[XLEN-1]=0
2016-06-09 Jonathan Neuschäfermake check: Fail if the tests failed
2016-06-09 Tim NewsomeFix 2 bugs in Debug ROM: (#52)
2016-06-09 Andrew WatermanAdd degenerate HW breakpoint implementation
2016-06-03 Tim NewsomeKeep DCSR_XDEBUGVER unsigned.
2016-06-03 neuschaeferMinor usability improvements (#48)
2016-06-03 Tim NewsomeDCSR cause was moved, bug debug ROM wasn't updated
2016-06-02 Tim NewsomeFix 'make check' when run from build directory.
2016-06-01 Andrew WatermanFix build when not building inside root directory
2016-06-01 Andrew WatermanAdd gitignore
2016-06-01 Tim NewsomeMove sethaltnot and cleardebint.
2016-05-24 Tim NewsomeNew encoding.h for new CSR addresses.
2016-05-24 Tim NewsomeMove cleardebint, per spec.
2016-05-23 Tim NewsomeUse .word for mret, for now.
2016-05-23 Tim NewsomeChange DCSR bits to match spec.
2016-05-23 Tim NewsomeKill spike as soon as the test is done with it.
2016-05-23 Tim NewsomeLink standalone programs at 0x80010000.
2016-05-23 Tim NewsomeTurn off debugging.
2016-05-23 Tim NewsomeTell gdb we can handle large packets.
2016-05-23 Tim NewsomeFix writing odd numbers of bytes to odd addresses.
2016-05-23 Tim NewsomeExceptions in Debug Mode don't update any regs.
2016-05-23 Tim NewsomeIgnore MPRV in Debug Mode.
2016-05-23 Tim NewsomeWrite test for downloading a mostly random program
2016-05-23 Tim NewsomeRemove already-implemented TODO.
2016-05-23 Tim NewsomeMove debug rom link map to the right place.
2016-05-23 Tim NewsomeRemove obsolete TODO.
2016-05-23 Tim NewsomeImplement ebreak[mhsu].
2016-05-23 Tim NewsomeRemove dependency on include file in my homedir.
2016-05-23 Tim NewsomeForce gdb to not print entry values.
2016-05-23 Tim Newsomemprv test now breaks like it's supposed to.
2016-05-23 Tim NewsomeDeal with escapes that gdb sends in binary data.
2016-05-23 Tim NewsomeMake -H halt the core right out of reset.
2016-05-23 Tim NewsomeHalt when gdb user hits ^C.
2016-05-23 Tim NewsomeMake sure to fence.i after setting/clearing a swbp
2016-05-23 Tim NewsomeImplemented register writes.
2016-05-23 Tim NewsomeFix reading CSRs.
2016-05-23 Tim NewsomeSingle step appears to work.
2016-05-23 Tim NewsomeSoftware breakpoints sort of work.
2016-05-23 Tim NewsomeUse fence.i in Debug ROM.
2016-05-23 Tim NewsomeFix off-by-two in general read registers.
2016-05-23 Tim NewsomeWalk page tables to translate addresses.
2016-05-23 Tim NewsomeTurn operation into a queue,
2016-05-23 Tim NewsomeRemove unused code.
2016-05-23 Tim NewsomeSave/restore mstatus, too.
2016-05-23 Tim NewsomeIgnore more files.
2016-05-23 Tim NewsomeProperly read s0/s1.
2016-05-23 Tim NewsomeAdd dret.
2016-05-23 Tim NewsomeImplement memory writes.
2016-05-23 Tim NewsomeImplement single memory read access.
2016-05-23 Tim NewsomeProperly save/restore dpc, mcause, mbadaddr.
2016-05-23 Tim NewsomeExceptions in Debug Mode, stay in Debug Mode.
2016-05-23 Tim NewsomeRemove debug printfs.
2016-05-23 Tim NewsomeHave Debug memory kind of working again.
2016-05-23 Tim NewsomeRead FP registers, and general CSRs*
2016-05-23 Tim NewsomeContinue works well enough for DebugTest.test_exit
2016-05-23 Tim NewsomeFix race using fence.
2016-05-23 Tim NewsomeRefactor how we track in-progress operations.
2016-05-23 Tim Newsomegdb can attach and read the PC:
2016-05-23 Tim Newsomeprocessor_t unfriends gdbserver_t.
2016-05-23 Tim NewsomeCorrectly read PC on halt.
2016-05-23 Tim NewsomeFix store to clear debug interrupt.
2016-05-23 Tim NewsomeAdd debug_module bus device.
2016-05-23 Tim NewsomeROM -> RAM -> ROM, waiting for debug int.
2016-05-23 Tim NewsomeMake sure to translate Debug RAM addresses also.
next