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yosys.git
2015-02-21
Clifford Wolf
Added "sat -tempinduct-baseonly -tempinduct-inductonly"
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2015-02-21
Clifford Wolf
Fixed basecase init for "sat -tempinduct"
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2015-02-21
Clifford Wolf
Fixed "flatten" for non-pre-derived modules
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2015-02-21
Clifford Wolf
Hotfix for yosysjs/demo03.html
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2015-02-21
Clifford Wolf
YosysJS: Wait for Viz to load
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2015-02-21
Clifford Wolf
Replaced ezDefaultSAT with ezSatPtr
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2015-02-21
Clifford Wolf
Catch constants assigned to cell outputs in "flatten"
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2015-02-20
Clifford Wolf
Added deep recursion warning to AST simplify
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2015-02-20
Clifford Wolf
Parser support for complex delay expressions
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2015-02-19
Clifford Wolf
YosysJS firefox fixes
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2015-02-19
Clifford Wolf
YosysJS stuff
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2015-02-19
Clifford Wolf
format fixes in "sat -dump_json"
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2015-02-19
Clifford Wolf
Added "sat -dump_json" (WaveJSON format)
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2015-02-19
Clifford Wolf
Changed "show" defaults for Win32
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2015-02-18
Clifford Wolf
Convert floating point cell parameters to strings
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2015-02-18
Clifford Wolf
Fixed clang (svn trunk) warnings
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2015-02-18
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-02-18
Clifford Wolf
Added "select %xe %cie %coe"
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2015-02-17
Clifford Wolf
wreduce help typo fix
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2015-02-17
Clifford Wolf
CodingReadme
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2015-02-16
Clifford Wolf
YosysJS fixes for firefox
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2015-02-16
Clifford Wolf
More YosysJS stuff
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2015-02-16
Clifford Wolf
Added YosysJS wrapper
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2015-02-16
Clifford Wolf
Bugfix in wreduce
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2015-02-15
Clifford Wolf
More yosys.js improvements
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2015-02-15
Clifford Wolf
Added Viz to yosys.js
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2015-02-15
Clifford Wolf
Added yosys.js FS support
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2015-02-15
Clifford Wolf
More emcc stuff
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2015-02-15
Clifford Wolf
Improved yosys.js example
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2015-02-15
Clifford Wolf
Added "stat" to "synth" and "synth_xilinx"
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2015-02-15
Clifford Wolf
Added final checks to "synth" and "synth_xilinx"
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2015-02-15
Clifford Wolf
Added "check -noinit"
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2015-02-15
Clifford Wolf
Cosmetic fixes in "hierarchy" for blackbox modules
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2015-02-15
Clifford Wolf
More emscripten stuff, Added example app
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2015-02-15
Clifford Wolf
Fixed default EMCCFLAGS
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2015-02-14
Clifford Wolf
Smaller default parameters in $mem simlib model
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2015-02-14
Clifford Wolf
Fixed "stat" handling of blackbox modules
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2015-02-14
Clifford Wolf
Various fixes for memories with offsets
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2015-02-14
Clifford Wolf
Added $meminit support to "memory" command
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2015-02-14
Clifford Wolf
Added $meminit test case
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2015-02-14
Clifford Wolf
Added "read_verilog -nomeminit" and "nomeminit" attribute
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2015-02-14
Clifford Wolf
Creating $meminit cells in verilog front-end
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2015-02-14
Clifford Wolf
Added $meminit cell type
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2015-02-14
Clifford Wolf
Fixed handling of "//" in filenames in verilog pre...
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2015-02-13
Clifford Wolf
Fixed "write_verilog -attr2comment" handling of "*...
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2015-02-13
Clifford Wolf
hotfix in "check" command
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2015-02-13
Clifford Wolf
Added "check" command
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2015-02-13
Clifford Wolf
Added AstNode::simplify() recursion counter
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2015-02-13
Clifford Wolf
Added EMCCFLAGS
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2015-02-12
Clifford Wolf
Some test related fixes
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2015-02-12
Clifford Wolf
Added "proc_dlatch"
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2015-02-10
Clifford Wolf
Less aggressive "share" defaults
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2015-02-10
Clifford Wolf
Improved read_verilog support for empty behavioral...
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2015-02-10
Clifford Wolf
Added "scc -expect <N> -nofeedback"
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2015-02-09
Clifford Wolf
Some hashlib improvements
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2015-02-09
Clifford Wolf
Various changes to release checklist
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2015-02-09
Clifford Wolf
Fixed creation of command reference in manual
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2015-02-09
Clifford Wolf
We are now in 0.5+ development
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2015-02-09
Clifford Wolf
Yosys 0.5
yosys-0.5
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2015-02-09
Clifford Wolf
Bugfix in "make vcxsrc"
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2015-02-09
Clifford Wolf
Updated command reference in manual
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2015-02-09
Clifford Wolf
Various presentation fixes
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2015-02-08
Clifford Wolf
Fixed iterator invalidation bug in "rename" command
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2015-02-08
Clifford Wolf
CodingReadme update
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2015-02-08
Clifford Wolf
Fixed bug in "show -format .."
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2015-02-08
Clifford Wolf
Added new APIs to changelog
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2015-02-08
Clifford Wolf
Fixed eval_select_op() api
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2015-02-08
Clifford Wolf
Added eval_select_args() and eval_select_op()
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2015-02-08
Clifford Wolf
Minor "make vgtest" changes
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2015-02-08
Clifford Wolf
Various ModIndex improvements
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2015-02-08
Clifford Wolf
Added Yosys 0.5 Changelog
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2015-02-08
Clifford Wolf
Various updates to CodingReadme
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2015-02-08
Clifford Wolf
Added equiv_add
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2015-02-07
Clifford Wolf
Ignore explicit assignments to constants in HDL code
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2015-02-07
Clifford Wolf
Fixed a bug with autowire bit size
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2015-02-07
Clifford Wolf
fixed typo
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2015-02-07
Clifford Wolf
Added "yosys-config --build modname.so cppsources.."
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2015-02-07
Clifford Wolf
Added SigSpec::has_const()
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2015-02-07
Clifford Wolf
Cleanup in add_share_file make macro
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2015-02-07
Clifford Wolf
Removed "make mklibyosys"
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2015-02-07
Clifford Wolf
Improved building of plugins
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2015-02-07
Clifford Wolf
Added "make uninstall"
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2015-02-07
Clifford Wolf
Added cell->known(), cell->input(portname), cell->outpu...
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2015-02-06
Clifford Wolf
Added "select -read"
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2015-02-05
Clifford Wolf
Auto-detect TCL version
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2015-02-04
Clifford Wolf
Added onehot attribute
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2015-02-04
Clifford Wolf
Fixed opt_clean performance bug
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2015-02-04
Clifford Wolf
Disabled (unused) Xilinx tristate buffers
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2015-02-03
Clifford Wolf
Using design->selected_modules() in opt_*
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2015-02-03
Clifford Wolf
Skip blackbox modules in design->selected_modules()
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2015-02-03
Clifford Wolf
Added "yosys -L logfile"
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2015-02-01
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-02-01
Clifford Wolf
no support for 6-series xilinx devices
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2015-02-01
Clifford Wolf
Merge pull request #48 from rubund/master
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2015-02-01
Clifford Wolf
Improved performance in equiv_simple
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2015-02-01
Ruben Undheim
Fixed typos found by lintian
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2015-02-01
Clifford Wolf
Removed old XST-based xilinx examples
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2015-02-01
Clifford Wolf
Added Xilinx example for Basys3 board
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2015-02-01
Clifford Wolf
Added EDIF backend support for multi-bit cell ports
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2015-02-01
Clifford Wolf
Added missing ports and parameters to xilinx brams
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