yosys.git
2019-12-31 Eddie HungAdd abc9_ops -prep_dff
2019-12-31 Eddie HungRestore count_outputs, move process check to abc
2019-12-31 Eddie HungFix struct name
2019-12-31 Eddie HungMerge remote-tracking branch 'origin/xaig_dff' into...
2019-12-31 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-12-30 Eddie Hungwrite_xaiger to use scratchpad for stats; cleanup abc9
2019-12-30 Eddie HungGrammar
2019-12-30 Eddie HungRemove submod changes
2019-12-30 Eddie HungUpdate timings for Xilinx S7 cells
2019-12-30 Eddie HungRemove unused
2019-12-30 Eddie HungDo not offset FD* box timings due to -46ps Tsu
2019-12-30 Eddie HungCall "proc" if processes inside whiteboxes
2019-12-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 Eddie HungAdd CHANGELOG entry, add abc9_{flop,keep} attr to README.md
2019-12-30 Eddie HungTidy up abc9_map.v
2019-12-30 Eddie HungAdd "synth_xilinx -dff" option, cleanup abc9
2019-12-30 Eddie HungGrammar
2019-12-30 Miodrag MilanovićMerge pull request #1589 from YosysHQ/iopad_default
2019-12-30 Eddie HungMerge pull request #1599 from YosysHQ/eddie/retry_1588
2019-12-30 Eddie HungMerge pull request #1600 from YosysHQ/eddie/cleanup_ecp5
2019-12-28 Miodrag MilanovicFix new tests
2019-12-28 Miodrag MilanovicMerge remote-tracking branch 'origin/master' into iopad...
2019-12-28 Miodrag MilanovicMake test without iopads
2019-12-28 Miodrag MilanovicRevert "Fix xilinx tests, when iopads are default"
2019-12-28 Eddie Hungabc9_techmap -> _map; called from abc9 script pass...
2019-12-28 Eddie HungRename abc9.cc -> abc9_techmap.cc
2019-12-28 Eddie HungUpdate resource count
2019-12-28 Eddie HungNitpick cleanup for ecp5
2019-12-28 Eddie HungAdd #1598 testcase
2019-12-28 Eddie Hungwrite_xaiger: inherit port ordering from original module
2019-12-28 Eddie HungRevert "Merge pull request #1598 from YosysHQ/revert...
2019-12-27 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-12-27 Eddie Hungwrite_xaiger: simplify c{i,o}_bits
2019-12-27 David ShahMerge pull request #1598 from YosysHQ/revert-1588-eddie...
2019-12-27 David ShahRevert "write_xaiger: only instantiate each whitebox...
2019-12-27 Eddie HungReally fix it!
2019-12-27 Eddie Hungwrite_xaiger: fix arrival times for non boxes
2019-12-25 Miodrag Milanovicfixed invalid char
2019-12-25 Marcin Kościelnickiiopadmap: Emit tristate buffers with const OE for some...
2019-12-25 Marcin KościelnickiMerge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
2019-12-25 Marcin KościelnickiMinor nit fixes
2019-12-23 Eddie HungAdd DSP cascade tests
2019-12-23 Eddie HungFix OPMODE for PCIN->PCOUT cascades in xc6s, check...
2019-12-23 Eddie HungFix CEA/CEB check
2019-12-23 Eddie HungFix checking CE[AB] and for direct connections
2019-12-23 Eddie HungSupport unregistered cascades for A and B inputs
2019-12-23 Eddie HungAdd DSP48A* PCOUT -> PCIN cascade support
2019-12-23 Marcin Kościelnickixilinx: Test our DSP48A/DSP48A1 simulation models.
2019-12-23 Eddie HungDisable clock domain partitioning in Yosys pass, let...
2019-12-23 Eddie Hungwrite_xaiger to opt instead of just clean whiteboxes
2019-12-22 Marcin Kościelnickixilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-21 Miodrag MilanovicAddressed review comments
2019-12-21 Miodrag Milanoviciopad no op for compatibility with old scripts
2019-12-21 Miodrag MilanovicFix xilinx tests, when iopads are default
2019-12-21 Miodrag MilanovicMake iopad option default for all xilinx flows
2019-12-20 Eddie HungMerge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
2019-12-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 Eddie HungAdd abc9_arrival times for RAM{32,64}M
2019-12-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 Eddie HungAdd RAM{32,64}M to abc9_map.v
2019-12-20 Eddie HungPut specify/endspecify inside ``
2019-12-20 Eddie HungMerge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
2019-12-20 Eddie Hungwrite_xaiger: only instantiate each whitebox cell type...
2019-12-20 Eddie HungMerge pull request #1587 from YosysHQ/revert-1558-eddie...
2019-12-20 Eddie HungRevert "Optimise write_xaiger"
2019-12-20 Graham EdgecombeFix linking with Python 3.8
2019-12-20 Graham EdgecombeAdd PYTHON_CONFIG variable to the Makefile
2019-12-19 Eddie HungAdd RAM{32,64}M to abc9_map.v
2019-12-19 Eddie HungSplit into $__ABC9_ASYNC[01], do not add cell->type...
2019-12-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 Eddie HungMerge pull request #1581 from YosysHQ/clifford/fix1565
2019-12-19 Eddie HungMerge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
2019-12-19 Eddie HungMerge pull request #1569 from YosysHQ/eddie/fix_1531
2019-12-19 Eddie HungMerge pull request #1571 from YosysHQ/eddie/fix_1570
2019-12-19 Marcin Kościelnickixilinx: Add simulation models for remaining CLB primitives.
2019-12-19 Marcin Kościelnickixilinx_dffopt: Keep order of LUT inputs.
2019-12-18 Eddie HungBump ABC again
2019-12-18 Eddie HungInterpret "abc9 -lut" as lut string only if [0-9:]
2019-12-18 Eddie HungAdd "scratchpad" to CHANGELOG
2019-12-18 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-12-18 David ShahMerge pull request #1563 from YosysHQ/dave/async-prld
2019-12-18 Eddie HungMerge pull request #1572 from nakengelhardt/scratchpad_pass
2019-12-18 Eddie HungMerge pull request #1584 from YosysHQ/mwk/xilinx-flaky...
2019-12-18 Marcin Kościelnickitests/xilinx: fix flaky mux test
2019-12-18 Marcin Kościelnickixilinx: Add xilinx_dffopt pass (#1557)
2019-12-18 Marcin Kościelnickixilinx: Improve flip-flop handling.
2019-12-18 Clifford WolfSend people to symbioticeda.com instead of verific.com
2019-12-18 N. Engelhardtuse extra_args
2019-12-18 Eddie HungRemove &verify -s
2019-12-18 Eddie HungBump ABC for upstream fix
2019-12-18 Eddie HungUse pool<> instead of std::set<> to preserver ordering
2019-12-17 Eddie Hungaiger frontend to user shorter, $-prefixed, names
2019-12-17 Eddie HungCleanup xaiger, remove unnecessary complexity with...
2019-12-17 Eddie Hungread_xaiger to cope with optional '\n' after 'c'
2019-12-17 Clifford WolfFix sim for assignments with lhs<rhs size, fixes #1565
2019-12-17 Eddie HungCleanup
2019-12-17 Eddie HungDo not sigmap
2019-12-17 Eddie HungRevert "Use sigmap signal"
2019-12-17 Eddie HungMerge pull request #1574 from YosysHQ/eddie/xilinx_lutram
2019-12-17 Eddie HungMerge pull request #1521 from dh73/diego/memattr
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