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yosys.git
2020-05-28
Xiretza
Add flooring modulo operator
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2020-05-28
whitequark
Merge pull request #2095 from rswarbrick/hier-typo
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2020-05-28
Rupert Swarbrick
Fix small typos in documentation for hierarchy command
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2020-05-28
whitequark
Merge pull request #2091 from boqwxp/printattrs
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2020-05-28
whitequark
Merge pull request #2051 from Xiretza/makefile-cd-warning
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2020-05-28
whitequark
Merge pull request #2031 from epfl-vlsc/master
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2020-05-28
whitequark
Merge pull request #2063 from boqwxp/techmapped-firrtl
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2020-05-28
whitequark
Merge pull request #2088 from rswarbrick/count-at
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2020-05-28
whitequark
Merge pull request #2087 from rswarbrick/lex-warn
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2020-05-28
whitequark
Merge pull request #2086 from rswarbrick/sigbit
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2020-05-28
whitequark
Merge pull request #2084 from rswarbrick/c_str
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2020-05-28
Alberto Gonzalez
printattrs: Simplify `get_indent_str()`.
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2020-05-27
Alberto Gonzalez
printattrs: Refactor indentation string building for...
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2020-05-27
Alberto Gonzalez
printattrs: Add test.
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2020-05-27
Alberto Gonzalez
printattrs: Use `flags` to pretty-print the `RTLIL...
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2020-05-27
Alberto Gonzalez
misc: Add `printattrs` command.
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2020-05-26
whitequark
Merge pull request #2090 from whitequark/cxxrtl-fixes
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2020-05-26
whitequark
cxxrtl: make logging a little bit nicer.
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2020-05-26
whitequark
cxxrtl: add missing parts of commit 281c9685.
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2020-05-26
Rupert Swarbrick
Silence spurious warning in Verilog lexer when compilin...
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2020-05-26
Rupert Swarbrick
Minor optimisation in Module::wire() and Module::cell()
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2020-05-26
Rupert Swarbrick
Use default copy constructor for RTLIL::SigBit
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2020-05-26
Rupert Swarbrick
Use c_str(), not str() for IdString/std::string ==...
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2020-05-25
Eddie Hung
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
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2020-05-25
Eddie Hung
tests: xilinx macc test to have initval, shorten BMC...
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2020-05-25
Eddie Hung
xilinx: tidy up cells_sim.v a little
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2020-05-25
Eddie Hung
Merge pull request #2044 from YosysHQ/eddie/fix2037
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2020-05-25
Eddie Hung
verilog: move attr from simple_behav_stmt to its childr...
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2020-05-25
Eddie Hung
test: add attribute-before-stmt test from @nakengelhardt
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2020-05-25
Eddie Hung
verilog: do not warn for attributes on null statements
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2020-05-25
Eddie Hung
tests: add an generate-else test too
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2020-05-25
Eddie Hung
verilog: handle empty generate statement by removing...
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2020-05-25
Eddie Hung
verilog: fix #2037 by permitting (and freeing) attribut...
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2020-05-25
Eddie Hung
tests: add #2037 testcase
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2020-05-25
clairexen
Merge pull request #2015 from boqwxp/qbfsat-bisection
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2020-05-24
Eddie Hung
Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanup
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2020-05-24
Eddie Hung
xaiger: add testcase
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2020-05-24
Eddie Hung
xaiger: do not derive cells
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2020-05-23
Eddie Hung
Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanup
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2020-05-23
Eddie Hung
ecp5: cleanup unused +/ecp5/abc9_model.v
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2020-05-23
Alberto Gonzalez
qbfsat: Remove cruft inadvertently left untouched in...
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2020-05-23
Alberto Gonzalez
qbfsat: Add bisection mode and make it the default.
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2020-05-22
whitequark
Merge pull request #2072 from whitequark/cxxrtl-dont...
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2020-05-22
whitequark
cxxrtl: get rid of -O5 aka `opt_clean -purge` optimizat...
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2020-05-22
Eddie Hung
abc9_ops: update comment
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2020-05-21
Eddie Hung
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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2020-05-21
Eddie Hung
Update frontends/verilog/verilog_parser.y
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2020-05-21
Miodrag Milanović
Merge pull request #2059 from boqwxp/logger-vector...
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2020-05-20
N. Engelhardt
Merge pull request #2046 from PeterCrozier/trap
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2020-05-20
N. Engelhardt
Merge pull request #2054 from boqwxp/fix-smtbmc
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2020-05-19
Alberto Gonzalez
smtbmc: Fix typo in error message.
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2020-05-18
Marcelina Kościelnicka
Add force_downto and force_upto wire attributes.
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2020-05-18
Eddie Hung
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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2020-05-17
Alberto Gonzalez
firrtl: Accept techmapped cell types in FIRRTL backend.
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2020-05-17
Claire Wolf
Revert "Add support for non-power-of-two mem chunks...
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2020-05-15
Alberto Gonzalez
log: Use `dict` instead of `std::vector<std::pair>...
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2020-05-14
Eddie Hung
abc9: use (* abc9_keep *) instead of (* abc9_scc *...
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2020-05-14
Eddie Hung
verilog: attributes before task enable (but 13 s/r...
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2020-05-14
Eddie Hung
tests: attributes before task enable
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2020-05-14
Eddie Hung
Merge pull request #2055 from YosysHQ/eddie/logger_multiple
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2020-05-14
Eddie Hung
opt_expr: Sx to Sz; spotted by @Xiretza
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2020-05-14
Eddie Hung
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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2020-05-14
Eddie Hung
logger: clean up doc
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2020-05-14
Eddie Hung
abc9_ops: -prep_hier to create unmap module that remove...
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2020-05-14
Eddie Hung
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean...
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2020-05-14
Eddie Hung
Fix broken test when ignoring abc9_flop with init ...
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2020-05-14
Eddie Hung
abc9_ops/xaiger: further reducing Module::derive()...
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2020-05-14
Eddie Hung
Cleanup; reduce Module::derive() calls
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2020-05-14
Eddie Hung
ecp5: latches_map.v if *not* -asyncprld
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2020-05-14
Eddie Hung
ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un...
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2020-05-14
Eddie Hung
ecp5: fix rebase mistake
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2020-05-14
Eddie Hung
abc9: update to =_$abc9_flops pattern which includes...
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2020-05-14
Eddie Hung
abc9_ops: update docs
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2020-05-14
Eddie Hung
xilinx: gate specify/attributes from iverilog
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2020-05-14
Eddie Hung
abc9: only do +/abc9_map if `DFF
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2020-05-14
Eddie Hung
abc9: rework submod -- since it won't move (* keep...
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2020-05-14
Eddie Hung
ecp5: TRELLIS_FF bypass path only in async mode
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2020-05-14
Eddie Hung
timinginfo: ignore $specify2 cells if EN is false
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2020-05-14
Eddie Hung
xilinx/ice40/ecp5: zinit requires selected wires, so...
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2020-05-14
Eddie Hung
abc9_ops: move assert
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2020-05-14
Eddie Hung
abc9: put 'aigmap' back
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2020-05-14
Eddie Hung
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able...
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2020-05-14
Eddie Hung
abc9_ops: fix bypass boxes using (* abc9_bypass *)
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2020-05-14
Eddie Hung
abc9_ops: tidy up, suppress error if no boxes/holes
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2020-05-14
Eddie Hung
abc9_ops: -prep_delays to not insert delay box if input...
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2020-05-14
Eddie Hung
abc9_ops: cleanup; -prep_dff -> -prep_dff_submod
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2020-05-14
Eddie Hung
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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2020-05-14
Eddie Hung
abc9_ops: -reintegrate to handle $_FF_; cleanup
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2020-05-14
Eddie Hung
xaiger: no longer use nonstandard even/odd to designate...
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2020-05-14
Eddie Hung
aiger: -xaiger to return $_FF_ flops
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2020-05-14
Eddie Hung
abc9: not enough to techmap_fail on (* init=1 *), hide...
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2020-05-14
Eddie Hung
abc9: test to use box file instead of auto
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2020-05-14
Eddie Hung
abc9: restore selected_modules()
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2020-05-14
Eddie Hung
synth_*: no need to explicitly read +/abc9_model.v
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2020-05-14
Eddie Hung
Revert "Merge pull request #1917 from YosysHQ/eddie...
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2020-05-14
Eddie Hung
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
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2020-05-14
Eddie Hung
kernel: TimingInfo to clamp -ve setup/edge-sensitive...
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2020-05-14
Eddie Hung
abc9_ops: -prep_dff_map to error if async flop found
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2020-05-14
Eddie Hung
Uncomment negative setup times; clamp to zero for conne...
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2020-05-14
Eddie Hung
abc9: remove redundant wbflip
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