yosys.git
2019-04-17 Eddie HungFix spacing
2019-04-17 Eddie HungOptimise
2019-04-17 Eddie HungAdd SB_LUT4 to box library
2019-04-16 Eddie HungAdd ice40 box files
2019-04-16 Eddie Hungabc9 to output some more info
2019-04-16 Eddie HungCIs before PIs; also sort each cell's connections befor...
2019-04-16 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-16 Eddie HungPort from xc7mux branch
2019-04-16 Eddie HungRe-enable partsel.v test
2019-04-16 Eddie Hungabc9 to call "setundef -zero" behaving as for abc
2019-04-16 Eddie HungMerge pull request #939 from YosysHQ/revert895
2019-04-16 Eddie HungRevert #895
2019-04-16 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-16 Eddie HungMerge pull request #937 from YosysHQ/revert-932-eddie...
2019-04-16 Eddie HungRevert "Recognise default entry in case even if all...
2019-04-15 Eddie HungMerge pull request #936 from YosysHQ/README-fix-quotes
2019-04-15 whitequarkREADME: fix some incorrect quoting.
2019-04-13 Eddie HungForgot backslashes
2019-04-13 Eddie HungHandle __dummy_o__ and __const[01]__ in read_aiger...
2019-04-13 Eddie Hungabc to ignore __dummy_o__ and __const[01]__ when re...
2019-04-13 Eddie HungOutput __const0__ and __const1__ CIs
2019-04-13 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-04-13 Eddie HungFix inout handling for -map option
2019-04-12 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-04-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-12 Eddie HungUse -map instead of -symbols for aiger
2019-04-12 Eddie Hungci_bits and co_bits now a list, order is important...
2019-04-12 Eddie HungAlso cope with duplicated CIs
2019-04-12 Eddie HungWIP
2019-04-12 Eddie HungComment out
2019-04-12 Eddie HungAdd support for synth_xilinx -abc9 and ignore abc9...
2019-04-12 Eddie HungCope with an output having same name as an input (i...
2019-04-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-12 Eddie HungMerge pull request #928 from litghost/add_xc7_sim_models
2019-04-12 Keith RothmanRemove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
2019-04-12 Clifford WolfMerge pull request #933 from dh73/master
2019-04-12 Clifford WolfMerge pull request #932 from YosysHQ/eddie/fixdlatch
2019-04-12 DiegoFixing issues in CycloneV cell sim
2019-04-11 Eddie HungAdd default entry to testcase
2019-04-11 Eddie HungRecognise default entry in case even if all cases cover...
2019-04-11 Eddie HungAdd non-input bits driven by unrecognised cells as...
2019-04-10 Eddie Hungparse_aiger() to rename all $lut cells after "clean"
2019-04-09 Keith RothmanFix LUT6_2 definition.
2019-04-09 Keith RothmanAdd additional cells sim models for core 7-series prima...
2019-04-08 Eddie HungFix a few typos
2019-04-08 Eddie HungMore space fixing
2019-04-08 Eddie HungFix spacing
2019-04-08 Eddie HungMerge branch 'master' into xaig
2019-04-08 Clifford WolfMerge pull request #919 from YosysHQ/multiport_transp
2019-04-07 David Shahmemory_bram: Fix multiport make_transp
2019-04-05 Clifford WolfAdd "read_ilang -lib"
2019-04-04 Clifford WolfAdded missing argument checking to "mutate" command
2019-04-03 Eddie HungMerge pull request #913 from smunaut/fix_proc_mux
2019-04-03 Sylvain Munautproc_mux: Fix crash when trying to optimize non-existan...
2019-04-03 Clifford WolfMerge pull request #912 from YosysHQ/bram_addr_en
2019-04-03 Clifford WolfMerge pull request #910 from ucb-bar/memupdates
2019-04-02 David Shahmemory_bram: Consider read enable for address expansion...
2019-04-02 Eddie HungMerge pull request #895 from YosysHQ/pmux2shiftx
2019-04-01 Jim LawsonRefine memory support to deal with general Verilog...
2019-03-29 Clifford WolfMerge pull request #907 from YosysHQ/clifford/fix906
2019-03-29 Clifford WolfBuild Verilog parser with -DYYMAXDEPTH=100000, fixes...
2019-03-28 Clifford WolfMerge pull request #901 from trcwm/libertyfixes
2019-03-28 Clifford WolfMerge pull request #903 from YosysHQ/bram_reset_transp
2019-03-27 David Shahmemory_bram: Reset make_transp when growing read ports
2019-03-27 Niels MoseleyLiberty file parser now accepts superfluous ;
2019-03-27 Niels MoseleyLiberty file parser now accepts superfluous ;
2019-03-27 Niels MoseleyLiberty file parser now accepts superfluous ;
2019-03-27 Clifford WolfAdd "read -verific" and "read -noverific"
2019-03-27 Clifford WolfAdd "rename -output"
2019-03-27 Clifford WolfImprove "rename" help message
2019-03-26 Clifford WolfAdd "cutpoint -undef"
2019-03-26 Clifford WolfAdd "hdlname" attribute
2019-03-26 Clifford WolfFix "verific -extnets" for more complex situations
2019-03-25 Clifford WolfAdd "cutpoint" pass
2019-03-25 Eddie HungCreate one $shiftx per bit in width
2019-03-25 Clifford WolfMerge pull request #896 from YosysHQ/transp_fixes
2019-03-25 Clifford WolfMerge pull request #897 from trcwm/libertyfixes
2019-03-25 Niels Moseleyspaces -> tabs
2019-03-25 Niels MoseleyEOL is now accepted as ';' replacement on lines that...
2019-03-24 Niels MoseleyUpdated the liberty parser to accept [A:B] ranges ...
2019-03-24 David Shahmemory_bram: Fix multiclock make_transp
2019-03-23 Eddie HungAdd a pmux-to-shiftx optimisation to proc_mux
2019-03-23 Clifford WolfAdd "mutate -none -mode", "mutate -mode none"
2019-03-23 Clifford WolfAdd "mutate -s <filename>"
2019-03-23 Clifford WolfMerge pull request #893 from YosysHQ/clifford/btormeminit
2019-03-23 Clifford WolfAdd support for memory initialization to write_btor
2019-03-23 Clifford WolfFix BTOR output tags syntax in writye_btor
2019-03-23 Clifford WolfAdd RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend...
2019-03-22 Clifford WolfMerge pull request #889 from YosysHQ/clifford/fix888
2019-03-22 Clifford WolfMerge pull request #890 from YosysHQ/clifford/fix887
2019-03-22 David ShahMerge pull request #891 from YosysHQ/xilinx_keep
2019-03-22 David Shahxilinx: Add keep attribute where appropriate
2019-03-22 Clifford WolfTrim init attributes when resizing FFs in "wreduce...
2019-03-21 Clifford WolfFix mem2reg handling of memories with upto data ports...
2019-03-21 Clifford WolfImprove "read_verilog -dump_vlog[12]" handling of upto...
2019-03-21 Clifford WolfImprove read_verilog debug output capabilities
2019-03-19 Clifford WolfMerge pull request #885 from YosysHQ/clifford/fix873
2019-03-19 Clifford WolfAdd Xilinx negedge FFs to synth_xilinx dffinit call...
2019-03-19 Eddie HungMerge pull request #808 from eddiehung/read_aiger
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
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