yosys.git
2022-03-14 YRabbitgowin: add support for Double Data Rate primitives
2022-03-14 Miodrag MilanovićMerge pull request #3232 from YosysHQ/micko/fst2tb
2022-03-14 Miodrag MilanovicAdded fst2tb pass for generating testbench
2022-03-14 Claire XenMerge pull request #3213 from antonblanchard/abc-typo
2022-03-14 Miodrag MilanovicProper example code
2022-03-12 github-actions... Bump version
2022-03-11 Miodrag MilanovićMerge pull request #3229 from YosysHQ/micko/sim_date
2022-03-11 Miodrag MilanovićMerge pull request #3222 from zachjs/prune-linux-ci
2022-03-11 Miodrag MilanovićMerge pull request #3228 from YosysHQ/micko/disable_tests
2022-03-11 Claire Xenia... Add "sim -q" option
2022-03-11 Miodrag MilanovicAdd date parameter to enable full date/time and version...
2022-03-11 Claire Xenia... Small fix in "sim" help message
2022-03-11 Miodrag MilanovićMerge pull request #3226 from YosysHQ/micko/btor2witness
2022-03-11 Miodrag MilanovicFstData already do conversion to VCD
2022-03-11 Miodrag MilanovicSupport cell name in btor witness file
2022-03-11 Claire Xenia... Fix handling of some formal cells in btor back-end
2022-03-11 Miodrag Milanovichandle state names of $anyconst and $anyseq
2022-03-11 Zachary SnowPrune Linux CI builds
2022-03-11 Miodrag MilanovicProper write of memory data
2022-03-10 Miodrag MilanovicDisable tests on most of platforms
2022-03-10 github-actions... Bump version
2022-03-09 Loftyintel_alm: M10K write-enable is negative-true
2022-03-09 Miodrag MilanovicStart work on memory init
2022-03-09 Miodrag MilanovicFixes and error check
2022-03-07 Miodrag Milanoviccleanup
2022-03-07 Miodrag MilanovicError checks for aiger witness
2022-03-07 Miodrag Milanovicbtor2 witness co-simulation
2022-03-07 Miodrag MilanovićMerge pull request #3210 from rqou/json-signed
2022-03-05 github-actions... Bump version
2022-03-04 Miodrag MilanovićMerge pull request #3186 from nakengelhardt/smtbmc_sby_...
2022-03-04 Miodrag MilanovićMerge pull request #3206 from YosysHQ/micko/quote_remove
2022-03-04 Miodrag MilanovićMerge pull request #3207 from nakengelhardt/json_escape...
2022-03-04 Miodrag MilanovicNext dev cycle
2022-03-04 Miodrag MilanovicRelease version 0.15 yosys-0.15
2022-03-04 Miodrag MilanovicUpdate ABC
2022-03-04 Miodrag MilanovicUpdate documentation
2022-03-04 Miodrag MilanovićMerge pull request #3219 from YosysHQ/micko/quick_vcd
2022-03-04 Miodrag MilanovićMerge pull request #3220 from YosysHQ/claire/simstuff
2022-03-03 github-actions... Bump version
2022-03-02 Miodrag MilanovicAdd option to ignore X only signals in output
2022-03-02 Miodrag MilanovicWrite simulation files after simulation is performed
2022-03-02 Miodrag MilanovicUpdate CHANGELOG
2022-03-02 Claire XenMerge pull request #3224 from YosysHQ/micko/refactor
2022-03-02 Miodrag MilanovicCleanup
2022-03-01 github-actions... Bump version
2022-02-28 Miodrag MilanovicRefactor sim output writers
2022-02-28 Miodrag MilanovicQuick fix
2022-02-28 Claire Xenia... Add writing of aiw files to "sim" command
2022-02-28 Claire Xenia... Hotfix in AIGER witness reader state machine
2022-02-28 Miodrag MilanovicVCD reader support by using external tool
2022-02-28 Miodrag MilanovićMerge pull request #3216 from YosysHQ/claire/simstuff
2022-02-27 Miodrag MilanovicSupport extended aiw format
2022-02-25 Miodrag MilanovicFix for last clock edge data
2022-02-25 Claire Xenia... Experimental sim changes
2022-02-25 github-actions... Bump version
2022-02-24 YRabbitgowin: Remove unnecessary attributes
2022-02-24 YRabbitgowin: Add support for true differential output
2022-02-23 Anton Blanchardabc: Fix {I} and {P} substitution
2022-02-22 N. Engelhardtprint cell name for properties in yosys-smtbmc
2022-02-22 Claire XenMerge pull request #3211 from YosysHQ/micko/witness
2022-02-22 Claire XenMerge pull request #3197 from YosysHQ/claire/smtbmcfix
2022-02-22 Rjson: Add help message for `signed` field
2022-02-22 github-actions... Bump version
2022-02-21 Miodrag MilanovićMerge pull request #3203 from YosysHQ/micko/sim_ff
2022-02-21 Marcelina Kościelnickaecp5: Do not use specify in generate in cells_sim.v.
2022-02-21 Miodrag MilanovicFix handling of ce_over_srst
2022-02-18 N. Engelhardtfix handling of escaped chars in json backend and frontend
2022-02-18 Claire Xenia... Fix cycle 0 in aiger witness co-simulation
2022-02-18 Miodrag MilanovicChanged error message
2022-02-18 Miodrag MilanovicAdded AIGER witness file co simulation
2022-02-18 Miodrag Milanovicsimplify logic of handling flip-flops and latches
2022-02-17 Miodrag MilanovicReview cleanup
2022-02-16 Miodrag MilanovicRemove quotes if any from attribute
2022-02-16 Miodrag Milanovictest dlatchsr and adlatch
2022-02-16 Miodrag MilanovicAdded test cases
2022-02-16 Miodrag MilanovicAdd support for various ff/latch cells simulation
2022-02-16 github-actions... Bump version
2022-02-15 Miodrag MilanovićMerge pull request #3204 from YosysHQ/claire/update-abc
2022-02-15 Miodrag MilanovicBump ABC version
2022-02-15 github-actions... Bump version
2022-02-14 Zachary Snowverilog: support for time scale delay values
2022-02-14 Kamil RakoczyFix access to whole sub-structs (#3086)
2022-02-13 github-actions... Bump version
2022-02-12 Marcelina Kościelnickagowin: Add remaining block RAM blackboxes.
2022-02-12 github-actions... Bump version
2022-02-11 Zachary Snowverilog: fix dynamic dynamic range asgn elab
2022-02-11 Zachary Snowverilog: fix const func eval with upto variables
2022-02-11 Claire XenMerge pull request #2376 from nmoroze/clk2ff-better...
2022-02-11 Claire Xenia... Add a bit of flexibilty re trace length when processing...
2022-02-11 Miodrag MilanovićMerge pull request #3164 from zachjs/fix-ast-warn
2022-02-11 Claire XenMerge branch 'master' into clk2ff-better-names
2022-02-11 Claire XenMerge pull request #2019 from boqwxp/glift
2022-02-10 github-actions... Bump version
2022-02-09 Miodrag MilanovićMerge pull request #3193 from YosysHQ/micko/verific_f
2022-02-09 Miodrag MilanovicAdd ability to override verilog mode for verific -f...
2022-02-09 Marcelina Kościelnickagowin: Fix LUT RAM inference, add more models.
2022-02-09 Marcelina Kościelnickaecp5: Fix DPR16X4 sim model.
2022-02-08 github-actions... Bump version
2022-02-07 Miodrag MilanovicNext dev cycle
2022-02-07 Miodrag MilanovicRelease version 0.14 yosys-0.14
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