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yosys.git
2022-02-18
Claire Xenia...
Fix cycle 0 in aiger witness co-simulation
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2022-02-18
Miodrag Milanovic
Changed error message
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2022-02-18
Miodrag Milanovic
Added AIGER witness file co simulation
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2022-02-18
Miodrag Milanovic
simplify logic of handling flip-flops and latches
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2022-02-17
Miodrag Milanovic
Review cleanup
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2022-02-16
Miodrag Milanovic
test dlatchsr and adlatch
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2022-02-16
Miodrag Milanovic
Added test cases
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2022-02-16
Miodrag Milanovic
Add support for various ff/latch cells simulation
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2022-02-16
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2022-02-15
Miodrag Milanović
Merge pull request #3204 from YosysHQ/claire/update-abc
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2022-02-15
Miodrag Milanovic
Bump ABC version
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2022-02-15
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2022-02-14
Zachary Snow
verilog: support for time scale delay values
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2022-02-14
Kamil Rakoczy
Fix access to whole sub-structs (#3086)
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2022-02-13
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2022-02-12
Marcelina Kościelnicka
gowin: Add remaining block RAM blackboxes.
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2022-02-12
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2022-02-11
Zachary Snow
verilog: fix dynamic dynamic range asgn elab
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2022-02-11
Zachary Snow
verilog: fix const func eval with upto variables
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2022-02-11
Claire Xen
Merge pull request #2376 from nmoroze/clk2ff-better...
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2022-02-11
Miodrag Milanović
Merge pull request #3164 from zachjs/fix-ast-warn
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2022-02-11
Claire Xen
Merge branch 'master' into clk2ff-better-names
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2022-02-11
Claire Xen
Merge pull request #2019 from boqwxp/glift
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2022-02-10
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2022-02-09
Miodrag Milanović
Merge pull request #3193 from YosysHQ/micko/verific_f
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2022-02-09
Miodrag Milanovic
Add ability to override verilog mode for verific -f...
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2022-02-09
Marcelina Kościelnicka
gowin: Fix LUT RAM inference, add more models.
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2022-02-09
Marcelina Kościelnicka
ecp5: Fix DPR16X4 sim model.
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2022-02-08
github-actions...
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2022-02-07
Miodrag Milanovic
Next dev cycle
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2022-02-07
Miodrag Milanovic
Release version 0.14
yosys-0.14
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2022-02-07
Miodrag Milanovic
Update CHANGELOG and manual
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2022-02-07
Miodrag Milanović
Merge pull request #3185 from YosysHQ/micko/co_sim
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2022-02-07
github-actions...
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2022-02-06
Marcelina Kościelnicka
nexus: Fix arith_map CO signal.
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2022-02-04
Miodrag Milanovic
Error detection for co-simulation
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2022-02-04
Miodrag Milanovic
bug fix and cleanups
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2022-02-03
github-actions...
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2022-02-02
Miodrag Milanović
Merge pull request #3183 from YosysHQ/micko/nto1mux
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2022-02-02
Miodrag Milanovic
Use bmux for NTO1MUX
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2022-02-02
Miodrag Milanovic
Add test cases for co-simulation
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2022-02-02
Miodrag Milanović
Merge pull request #3182 from yrabbit/wip-doc2
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2022-02-02
YRabbit
Correct a typo in the manual
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2022-02-02
Miodrag Milanovic
Fix Visual Studio build
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2022-02-02
Miodrag Milanovic
respect hide_internal flag
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2022-02-02
Miodrag Milanovic
unify cycles counting and cleanup
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2022-02-02
Miodrag Milanovic
added stimulus mode and param check
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2022-02-02
Scott Thibault
Update comment
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2022-02-02
Scott Thibault
Fix unextend method for signed constants
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2022-01-31
Miodrag Milanovic
error when no signal found
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2022-01-31
Miodrag Milanović
Merge pull request #3176 from higuoxing/fix-ref-manual
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2022-01-31
Miodrag Milanovic
Cleanup
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2022-01-31
Miodrag Milanovic
Compare bits when not all are defined
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2022-01-31
Miodrag Milanovic
Cleanup
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2022-01-31
Miodrag Milanovic
message update
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2022-01-31
Miodrag Milanovic
Display simulation time data
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2022-01-31
Miodrag Milanovic
Use edges when explicit
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2022-01-31
Miodrag Milanovic
Updating initial state and checks
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2022-01-31
Miodrag Milanovic
Fix scope
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2022-01-31
github-actions...
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2022-01-31
Marcelina Kościelnicka
verilog backend: Emit a `wire` for ports as well.
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2022-01-30
Xing GUO
Fix the help message of synth_quicklogic.
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2022-01-30
Marcelina Kościelnicka
opt_reduce: Add $bmux and $demux optimization patterns.
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2022-01-29
github-actions...
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2022-01-28
Marcelina Kościelnicka
Add $bmux and $demux cells.
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2022-01-28
Miodrag Milanovic
check if stop before start
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2022-01-28
Miodrag Milanovic
set initial state, only flip-flops
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2022-01-28
Miodrag Milanovic
ignore not found private signals
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2022-01-28
Miodrag Milanovic
preserve VCD mangled names
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2022-01-28
Miodrag Milanovic
detect edges even when x
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2022-01-28
Miodrag Milanovic
recursive check
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2022-01-28
Miodrag Milanovic
cleanup
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2022-01-28
Miodrag Milanovic
Do actual compare
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2022-01-28
Miodrag Milanovic
Fix for limit_range_end when not writing vcd
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2022-01-28
Miodrag Milanovic
Add more options and time handling
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2022-01-28
Marcelina Kościelnicka
opt_dff: Don't mutate muxes while ModWalker is active.
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2022-01-28
Marcelina Kościelnicka
kernel/mem: Add read-first semantic emulation code.
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2022-01-28
github-actions...
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2022-01-27
Marcelina Kościelnicka
manual: Fix a custom pass example.
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2022-01-27
Marcelina Kościelnicka
memory_bram: Make use of new mem emulation functions...
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2022-01-27
Marcelina Kościelnicka
kernel/mem: Add functions to emulate read port enable...
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2022-01-27
github-actions...
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2022-01-26
Miodrag Milanović
change to windows-2019
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2022-01-26
Miodrag Milanovic
update version
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2022-01-26
Miodrag Milanovic
Display values of outputs
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2022-01-26
Miodrag Milanovic
Fix tabs/spaces
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2022-01-26
Miodrag Milanovic
Check if stimulated
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2022-01-26
Miodrag Milanovic
Read fst and use data to set inputs
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2022-01-26
Miodrag Milanovic
Add fstdata helper class
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2022-01-26
Miodrag Milanovic
Cleanup of config to support platforms
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2022-01-26
Miodrag Milanovic
Add ability to write to FST file
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2022-01-25
Miodrag Milanovic
Add FST library
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2022-01-20
github-actions...
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2022-01-19
gatecat
nexus: Fix BB sim model
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2022-01-19
Miodrag Milanovic
Removed dbits 8 since 9 will always be picked
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2022-01-19
Miodrag Milanović
Merge pull request #3120 from Icenowy/anlogic-bram
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2022-01-18
Zachary Snow
fix dumpAst() compilation warning
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2022-01-18
github-actions...
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2022-01-17
Miodrag Milanović
Merge pull request #3162 from YosysHQ/mmicko/windows_gu...
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2022-01-17
Miodrag Milanović
Update guidelines/Windows
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