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yosys.git
2019-08-26
Eddie Hung
Merge branch 'master' into eddie/xilinx_srl
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2019-08-26
Eddie Hung
Remove dupe in CHANGELOG, missing end quote
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2019-08-26
Clifford Wolf
Merge tag 'yosys-0.9'
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2019-08-26
Clifford Wolf
Yosys 0.9
yosys-0.9
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2019-08-25
Clifford Wolf
Merge pull request #1112 from acw1251/pyosys_sigsig_issue
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2019-08-24
Clifford Wolf
Merge pull request #1327 from YosysHQ/clifford/pmgen
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2019-08-24
Eddie Hung
Create new $__XILINX_SHREG_ cell for variable length too
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2019-08-24
Eddie Hung
Do not allow Q of last cell of variable length SRL...
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2019-08-24
Eddie Hung
Also add first.Q to chain_bits since variable length
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2019-08-24
Eddie Hung
Do not enforce !EN_POLARITY on $dffe
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2019-08-24
Eddie Hung
Create new cell for fixed length SRL
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2019-08-24
Eddie Hung
Cleanup FDRE matching
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2019-08-23
Eddie Hung
Add undocumented feature
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2019-08-23
Eddie Hung
Oops don't need a finally block
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2019-08-23
Eddie Hung
Keep track of bits in variable length chain, to check...
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2019-08-23
Eddie Hung
Don't forget $dff has no EN
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2019-08-23
Eddie Hung
Same for variable length
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2019-08-23
Eddie Hung
Filter on en_port for fixed length
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2019-08-23
Eddie Hung
Check clock is consistent
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2019-08-23
Eddie Hung
Fix last_cell.D
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2019-08-23
Eddie Hung
Revert "Add a unique argument to pmgen's nusers()"
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2019-08-23
Eddie Hung
Revert "Fix polarity"
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2019-08-23
Eddie Hung
Fix polarity
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2019-08-23
Eddie Hung
Check for non unique nusers/fanouts
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2019-08-23
Eddie Hung
Add a unique argument to pmgen's nusers()
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2019-08-23
Eddie Hung
Update doc
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2019-08-23
Eddie Hung
Remove (* init *) entry when consumed into SRL
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2019-08-23
Eddie Hung
indo -> into
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2019-08-23
Eddie Hung
indo -> into
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2019-08-23
Eddie Hung
Forgot to slice
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2019-08-23
Eddie Hung
Cope with possibility that D could connect to Q on...
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2019-08-23
Eddie Hung
Revert earliest to gcc-4.8, compile iverilog with defau...
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2019-08-23
Eddie Hung
Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbo...
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2019-08-23
Eddie Hung
Remove .0 from clang-8.0
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2019-08-23
Eddie Hung
Bump to gcc-5 as `__warn_memset_zero_len' symbol not...
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2019-08-23
Eddie Hung
bionic -> xenial as its on whitelist
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2019-08-23
Eddie Hung
Bump gcc from 4.8 to 4.9 as undefined reference
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2019-08-23
Eddie Hung
Mention shregmap -tech xilinx is superseded
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2019-08-23
Eddie Hung
xilinx_srl now copes with word-level flops $dff{,e}
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2019-08-23
Eddie Hung
xilinx_srl to use 'slice' features of pmgen for word...
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmgen...
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-23
Eddie Hung
Forgot one
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2019-08-23
Eddie Hung
Put abc_* attributes above port
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2019-08-23
Miodrag Milanovic
Make macOS depenency clear
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2019-08-23
Eddie Hung
Merge pull request #1326 from mmicko/doc-update
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2019-08-23
Clifford Wolf
Fix port hanlding in pmgen
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2019-08-23
Clifford Wolf
Add pmgen slices and choices
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2019-08-23
Miodrag Milanovic
Make macOS depenency clear
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2019-08-22
Eddie Hung
Do not propagate mem2reg attribute through to result
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2019-08-22
Eddie Hung
In sat: 'x' in init attr should not override constant
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2019-08-22
Eddie Hung
Remove Xilinx test
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2019-08-22
Eddie Hung
Actually, there might not be any harm in updating sigmap...
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2019-08-22
Eddie Hung
Add comment as per @cliffordwolf
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2019-08-22
Eddie Hung
Add shregmap -tech xilinx test
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2019-08-22
Eddie Hung
Revert "Try way that doesn't involve creating a new...
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2019-08-22
Eddie Hung
Try way that doesn't involve creating a new wire
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2019-08-22
Eddie Hung
If d_bit already in sigbit_chain_next, create extra...
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2019-08-22
Eddie Hung
Spelling
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2019-08-22
Miodrag Milanovic
do not require boost if pyosys is not used
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2019-08-22
Chris Shucksmith
require tcl-tk in Brewfile
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2019-08-22
Eddie Hung
Merge pull request #1322 from mmicko/pyosys_osx
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2019-08-22
Eddie Hung
Add doc
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2019-08-22
Miodrag Milanovic
do not require boost if pyosys is not used
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2019-08-22
Eddie Hung
Merge pull request #1319 from TeaEngineering/shuckc...
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2019-08-22
Eddie Hung
Add copyright
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2019-08-22
Eddie Hung
Add CHANGELOG entry
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2019-08-22
Eddie Hung
Remove `shregmap -tech xilinx` additions
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2019-08-22
Eddie Hung
pmgen to also iterate over all module ports
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2019-08-22
Eddie Hung
Remove output_bits
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2019-08-22
Eddie Hung
Forgot to set ud_variable.minlen
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2019-08-22
Eddie Hung
Do not run xilinx_srl_pm in fixed loop
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2019-08-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
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2019-08-22
Clifford Wolf
Bump year in copyright notice
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2019-08-22
Clifford Wolf
Bump year in copyright notice
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2019-08-22
Clifford Wolf
Fix missing newline at end of file
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2019-08-22
Clifford Wolf
Merge pull request #1289 from mmicko/anlogic_fixes
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2019-08-22
Clifford Wolf
Fix missing newline at end of file
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2019-08-22
Clifford Wolf
Merge pull request #1281 from mmicko/efinix
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2019-08-22
Eddie Hung
Copy-paste typo
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2019-08-22
Chris Shucksmith
require tcl-tk in Brewfile
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2019-08-22
Eddie Hung
Respect opt_expr -keepdc as per @cliffordwolf
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2019-08-22
Eddie Hung
Handle $shift and Y_WIDTH > 1 as per @cliffordwolf
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2019-08-22
Eddie Hung
Add cover()
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2019-08-22
Eddie Hung
Canonical form
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2019-08-22
Clifford Wolf
Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg
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2019-08-22
Eddie Hung
Add test
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2019-08-22
Eddie Hung
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
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2019-08-22
Eddie Hung
Reuse var
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2019-08-22
Eddie Hung
Revert "Trim shiftx_width when upper bits are 1'bx"
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2019-08-22
Eddie Hung
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
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2019-08-22
Eddie Hung
Trim shiftx_width when upper bits are 1'bx
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2019-08-22
Eddie Hung
Add comment
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2019-08-22
Eddie Hung
Add variable length support to xilinx_srl
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2019-08-21
Eddie Hung
Rename pattern to fixed
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2019-08-21
Eddie Hung
attribute -> attr
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2019-08-21
Eddie Hung
Use Cell::has_keep_attribute()
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2019-08-21
Eddie Hung
abc9 to perform new 'map_ffs' before 'map_luts'
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