litex.git
2015-04-04 Sebastien Bourdeauducqmibuild: support multiple specifications of include...
2015-04-02 Sebastien BourdeauducqMerge branch 'master' of github.com:m-labs/migen
2015-04-02 Yann Sionneaukc705: fix typo in platform file (LPC definition)
2015-04-02 Florent Kermarrecremove use of _r prefix on CSRs
2015-04-02 Florent Kermarrecmigen/bank/description: remove support of _r prefix...
2015-03-30 Florent Kermarrecremove redundant xilinx_strace_tailor.sh
2015-03-30 Sebastien Bourdeauducqmove xilinx_strace_tailor to tools
2015-03-30 Sebastien BourdeauducqRevert "migen: create VerilogConvert and EDIFConvert...
2015-03-30 Sebastien BourdeauducqRevert "migen/fhdl: pass fdict filename --> contents...
2015-03-30 Sebastien BourdeauducqRevert "migen/fhdl/specials: use fdict to pass memory...
2015-03-30 Florent Kermarrecmibuild/platforms: fix minispartan6
2015-03-30 Florent Kermarrecmigen/fhdl/specials: use fdict to pass memory initializ...
2015-03-30 Florent Kermarrecmigen/fhdl: pass fdict filename --> contents to specials
2015-03-30 Florent Kermarrecmigen: create VerilogConvert and EDIFConvert classes...
2015-03-29 Sebastien BourdeauducqMerge branch 'master' of github.com:m-labs/migen
2015-03-29 Sebastien Bourdeauducqplatforms/lx9_microboard,usrp_b100: fix bitgen opts
2015-03-29 Florent Kermarrecplatforms/kc705: fix .bin generation with ISE and Vivado
2015-03-29 Florent Kermarrecplatforms/kc705: add iMPACT programmer
2015-03-27 Sebastien BourdeauducqMerge branch 'master' of https://github.com/m-labs...
2015-03-27 Robert Jordensadd tool to build minimal xilinx toolchains
2015-03-27 Florent Kermarrecmibuild/sim: use the same architecture we use for other...
2015-03-22 Florent Kermarrecplatforms/minispartan6: add ftdi_fifo pins
2015-03-22 Florent Kermarrecplatforms/minispartan6: fix IOStandard/Slew, add FpgaPr...
2015-03-21 Florent Kermarrecmibuild/xilinx/programmer: add iMPACT programmer (for...
2015-03-21 Florent Kermarrecmibuild/platforms/minispartan6: adapt to recent changes...
2015-03-21 Florent Kermarrecmibuild/platforms/minispartan6: add device parameter...
2015-03-21 Florent Kermarrecmibuild/platforms: review and fix small mistakes
2015-03-21 Florent Kermarrecmibuild/platforms: add minispartan6 (from Matt O'Gorman)
2015-03-21 Robert Jordenstest_actor: add unittests for SimActor
2015-03-21 Robert Jordenssim: keep track of unreferenced items
2015-03-19 Robert Jordenspipistrello: switch is a button
2015-03-19 Robert Jordenspipistrello: compress and load bitstream at 6MHz
2015-03-19 Robert Jordenspipistrello: rename sdram->ddram
2015-03-18 Sebastien Bourdeauducqfhdl/verilog: fix dummy signal initial event
2015-03-18 Florent Kermarrecmibuild/lattice/diamond: add verilog include path ...
2015-03-18 Florent Kermarrecfhdl/specials/memory: use $readmemh to initialize memories
2015-03-18 Florent Kermarrecfhdl/verilog: change the way we initialize reg: reg...
2015-03-18 Florent Kermarrecfhdl/verilog: revert "fhdl/verilog: add simulation...
2015-03-18 Florent Kermarrecmigen/genlib/io: use 0 instead of Signal() for default...
2015-03-18 Sebastien BourdeauducqRevert "fhdl/verilog: do not use initial begin in _prin...
2015-03-17 Florent Kermarrecgenlib/io: add optional external rst to CRG
2015-03-17 Florent Kermarrecmibuild/platform/versa: fix clock_constraints
2015-03-17 Florent Kermarrecmibuild/lattice: use ODDRXD1 and new synthesis directive
2015-03-17 Florent Kermarrecfhdl/special: add optional synthesis directive (needed...
2015-03-17 Florent Kermarrecmibuild/lattice: add LatticeAsyncResetSynchronizer
2015-03-17 Florent Kermarrecmibuild/platforms/versa: add ethernet clock constraints
2015-03-17 Florent Kermarrecmibuild/platforms/versa: add rst_n
2015-03-17 Florent Kermarrecmibuild/lattice: fix LatticeDDROutput
2015-03-16 Florent Kermarrecfhdl/verilog: add simulation parameter to avoid simulat...
2015-03-16 Florent Kermarrecfhdl/verilog: do not use initial begin in _printinit...
2015-03-16 Florent Kermarrecmibuild/xilinx/common: add LatticeDDROutput
2015-03-16 Florent Kermarrecmibuild/xilinx/common: add XilinxDDROutput
2015-03-16 Florent Kermarrecmigen/genlib/io: add DDRInput and DDROutput
2015-03-16 Florent Kermarrecmibuild/platforms: add ethernet to versa
2015-03-16 Florent Kermarrecmibuild/platforms: add user_dip_btn to versa
2015-03-16 Florent Kermarrecmibuild/lattice: use new Toolchain/Platform architecture
2015-03-16 Florent Kermarrecmibuild/altera: use new Toolchain/Platform architecture
2015-03-16 Florent Kermarrecmibuild: add initial Lattice Diamond support (with...
2015-03-14 Sebastien Bourdeauducqmove pytholite to separate repos
2015-03-14 Sebastien Bourdeauducqfhdl/visit: fix TransformModule
2015-03-14 Sebastien Bourdeauducqmibuild/xilinx: export special_overrides dictionary
2015-03-13 Sebastien Bourdeauducqmibuild/xilinx: remove obsolete CRG_DS
2015-03-13 Sebastien Bourdeauducqmibuild: sanitize default clock management
2015-03-13 Sebastien Bourdeauducqmibuild: get rid of Platform factory function, cleanup
2015-03-12 Florent Kermarrecmigen/genlib/io: add DifferentialOutput and Xilinx...
2015-03-12 Florent Kermarrecgenlib/io.py: fix copy/paste error (thanks rjo)
2015-03-12 Florent Kermarrecmigen/genlib: add io.py to define generic I/O specials...
2015-03-10 Florent Kermarrecmibuild/sim: clean up (thanks sb)
2015-03-10 Sebastien Bourdeauducqmibuild/sim/dut_tb: fix permissions
2015-03-09 Florent Kermarrecmibuild/sim: get serial dev from /tmp/simserial
2015-03-09 Florent Kermarrecmibuild/sim: add support for pty
2015-03-09 Florent Kermarrecmibuild/sim: remove hack, the issue was in gateware...
2015-03-09 Florent Kermarrecgenlib/misc: add increment parameter to Counter
2015-03-09 Florent Kermarrecfhdl/module: use r.append() in _collect_submodules
2015-03-09 Florent Kermarrecfhdl/module: avoid flushing self._submodules and create...
2015-03-09 Florent Kermarrecmibuild/sim: clean up and move eth struct to sim
2015-03-09 Florent Kermarrecmibuild/sim: regroup console_tb/ethernet_tb in dut_tb
2015-03-09 Florent Kermarrecmibuild/sim: remove server and interact with tap direct...
2015-03-09 Robert Jordensvivado: permit resources without pins
2015-03-06 Florent Kermarrecmibuild/sim: able to visualize arp requests with wireshark
2015-03-06 Florent Kermarrecmibuild/sim: able to send ethernet frame from sim to...
2015-03-06 Florent Kermarrecmibuild/sim: add ethernet pins to verilor.py
2015-03-06 Florent Kermarrecplatforms/sim: add ethernet pins
2015-03-05 Sebastien Bourdeauducqgenlib/cordic: fix typos
2015-03-04 Florent Kermarrecgenlib/misc: fix missing *args in Counter
2015-03-03 Florent Kermarrecmibuild/sim/server_tb: use SERIAL_SINK_ACK
2015-03-03 Florent Kermarrecmibuild/sim: use /tmp/simsocket sockaddr for server
2015-03-03 Florent Kermarrecmibuild/sim: avoid updating end at each cycle (simulati...
2015-03-03 Florent Kermarrecmibuild/sim: simplify console_tb with sim struct
2015-03-03 Florent Kermarrecmibuild/sim: create server.py and server_tb (Proof...
2015-03-03 Sebastien Bourdeauducqxilinx/programmer/vivado: fix Linux support
2015-03-03 Sebastien Bourdeauducqplatforms/kc705: fix imports
2015-03-02 Florent KermarrecMerge branch 'master' of github.com/m-labs/migen
2015-03-02 Florent Kermarrecmibuild/sim/verilator: remove verilator_root, use ...
2015-03-02 Sebastien Bourdeauducqmibuild/sim: style fixes
2015-03-02 Florent Kermarrecmove dma_lasmi to MiSoC
2015-03-01 Florent Kermarreclasmi: simplify usage for the user (it's the job of...
2015-03-01 Florent Kermarrecmibuild: initial Verilator support
2015-03-01 Florent Kermarrecgenlib/misc: add FlipFlop, Counter, Timeout
2015-02-28 Sebastien Bourdeauducqplatforms/pipistrello: remove unconnected SDRAM pins
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