litex.git
2012-02-06 Sebastien Bourdeauducqfhdl: do not attempt slicing non-array signals to keep...
2012-02-06 Sebastien Bourdeauducqbank: event manager
2012-02-06 Sebastien Bourdeauducqbank: support registers larger than the bus word width
2012-02-06 Sebastien Bourdeauducqbank: refactoring
2012-02-06 Sebastien Bourdeauducqbank/csrgen: use enumerate
2012-02-05 Sebastien Bourdeauducqfhdl/structure: binary constant builder
2012-02-03 Sébastien BourdeauducqMerge pull request #2 from larsclausen/master
2012-02-02 Lars-Peter... Use enumerate(x) instead of zip(range(x), x)
2012-02-02 Lars-Peter... fhdl/namer: Add support for STORE_DEREF opcode
2012-02-02 Lars-Peter... Lower required python version to 3.1
2012-01-28 Sebastien Bourdeauducqexamples/wb_intercon: update to new APIs
2012-01-28 Sebastien Bourdeauducqfhdl/namer: extract variable names with bytecode inspection
2012-01-28 Sebastien Bourdeauducqfhdl: do not prefix instance signal names
2012-01-27 Sebastien BourdeauducqRemove explicit bus names and rely on the new automatic...
2012-01-27 Sebastien Bourdeauducqfhdl: support memory read enable
2012-01-27 Sebastien Bourdeauducqfhdl: make WRITE_FIRST default
2012-01-27 Sebastien Bourdeauducqdoc: memories
2012-01-27 Sebastien Bourdeauducqfhdl: memories working
2012-01-27 Sebastien Bourdeauducqfhdl/verilog: clean up signal classification and suppor...
2012-01-27 Sebastien Bourdeauducqfhdl/structure: memory description
2012-01-27 Sebastien Bourdeauducqdoc: cosmetic changes
2012-01-26 Sebastien Bourdeauducqdoc: ASMI description
2012-01-25 Sebastien BourdeauducqRemove duplicate logo
2012-01-25 Sebastien Bourdeauducqdoc: refactor
2012-01-21 Sebastien Bourdeauducqflow/ala: fix typo for And (thanks Lars)
2012-01-21 Sebastien BourdeauducqLogo
2012-01-20 Sebastien BourdeauducqUse meaningful class names
2012-01-20 Sebastien BourdeauducqInclude fragment pads in pre-naming dictionary
2012-01-20 Sebastien Bourdeauducqnamer/trace_back: behave on None code_context
2012-01-20 Sebastien BourdeauducqFix instance support
2012-01-20 Sebastien BourdeauducqInclude unused I/Os in pre-naming dictionary and regist...
2012-01-20 Sebastien BourdeauducqRemove NoContext
2012-01-19 Sebastien BourdeauducqOnly include context prefix when necessary
2012-01-19 Sebastien BourdeauducqFix disjoint namespace test
2012-01-19 Sebastien BourdeauducqAlways include last step in names
2012-01-19 Sebastien BourdeauducqNew naming system: second attempt
2012-01-16 Sebastien Bourdeauducqexamples/corelogic_conv: use two dividers
2012-01-16 Sebastien Bourdeauducqcorelogic/record: empty default name
2012-01-16 Sebastien BourdeauducqNew naming system beginning to work
2012-01-16 Sebastien Bourdeauducqfhdl: new naming system (broken)
2012-01-15 Sebastien Bourdeauducqactorlib/control: 'for' generator
2012-01-15 Sebastien Bourdeauducqdma_wishbone: small syntax simplification thanks to...
2012-01-15 Sebastien Bourdeauducqfhdl: allow None statements
2012-01-15 Sebastien Bourdeauducqwishbone_dma: convert to new endpoint API and fix some...
2012-01-15 Sebastien Bourdeauducqbus: list signals
2012-01-15 Sebastien Bourdeauducqflow: saner endpoint management
2012-01-13 Sebastien BourdeauducqWishbone: omit fixed LSBs
2012-01-10 Sebastien Bourdeauducqactorlib: Wishbone DMA read master (WIP)
2012-01-10 Sebastien Bourdeauducqrecord: return offset
2012-01-10 Sebastien Bourdeauducqflow: simplify actor fragment interface
2012-01-09 Sebastien Bourdeauducqrecord: support aligned flattening
2012-01-09 Sebastien Bourdeauducqcorelogic: FSM
2012-01-09 Sebastien Bourdeauducqrecord: cleanup
2012-01-09 Sebastien Bourdeauducqrecord: better exception code
2012-01-09 Sebastien Bourdeauducqrecord: preserve order
2012-01-09 Sebastien Bourdeauducqflow: draw network graph
2012-01-09 Sebastien Bourdeauducqflow: actor busy signal
2012-01-08 Sebastien BourdeauducqComposer (WIP)
2012-01-07 Sebastien Bourdeauducqendpoint: add _i/_o suffix on signal names
2012-01-07 Sebastien Bourdeauducqfhdl: better signal naming heuristic
2012-01-07 Sebastien Bourdeauducqconstant: equality
2012-01-07 Sebastien Bourdeauducqverilog: split comb block, use assign statements
2012-01-06 Sebastien Bourdeauducqconvtools -> tools
2012-01-06 Sebastien Bourdeauducqflow: network
2012-01-06 Sebastien Bourdeauducqrecord: compatibility check
2012-01-06 Sebastien Bourdeauducqflow: plumbing
2012-01-06 Sebastien Bourdeauducqactor: simplified automatic control
2012-01-06 Sebastien BourdeauducqALA: use records for tokens
2012-01-06 Sebastien BourdeauducqREADME: update copyright year
2012-01-06 Sebastien Bourdeauducqcorelogic: record
2012-01-06 Sebastien BourdeauducqSignal repr
2012-01-05 Sebastien BourdeauducqMerge branch 'master' of github.com:milkymist/migen
2012-01-05 Sebastien BourdeauducqConvert -> convert
2011-12-27 Alain Péteutsetup.py: fix to catch all modules
2011-12-24 Alain PéteutAdd setup script
2011-12-22 Sebastien Bourdeauducqexample: flow conversion
2011-12-22 Sebastien Bourdeauducqflow: sum and division actors
2011-12-22 Sebastien Bourdeauducqfhdl: encapsulate replicated constants
2011-12-22 Sebastien Bourdeauducqflow: actor class
2011-12-22 Sebastien Bourdeauducqcsr: use optree
2011-12-22 Sebastien Bourdeauducqcorelogic: operator tree
2011-12-21 Sebastien Bourdeauducqverilog: comb reset
2011-12-21 Sebastien Bourdeauducqverilog: break down Convert function
2011-12-21 Sebastien Bourdeauducqverilog: ignore variable property in combinatorial...
2011-12-21 Sebastien BourdeauducqConsistent names
2011-12-19 Sebastien BourdeauducqREADME: Flow
2011-12-19 Sebastien BourdeauducqREADME: Core Logic, Bus, Bank
2011-12-19 Sebastien BourdeauducqREADME: structure + FHDL description
2011-12-18 Sebastien Bourdeauducqexamples: remove old-style declarations
2011-12-18 Sebastien Bourdeauducqcorelogic: fix signal exports
2011-12-18 Sebastien Bourdeauducqfhdl: better matching of assignment
2011-12-18 Sebastien BourdeauducqRemove uses of declare_signal
2011-12-18 Sebastien Bourdeauducqfhdl: also take into account object attributes in _make...
2011-12-18 Sebastien Bourdeauducqfhdl: automatic signal name from assignment
2011-12-17 Sebastien Bourdeauducqbank: support raw registers
2011-12-17 Sebastien Bourdeauducqfhdl: fix series of if/elif/else
2011-12-17 Sebastien Bourdeauducq32-device, 8-bit CSR bus
2011-12-17 Sebastien Bourdeauducqverilog: get the simulator to run the combinatorial...
2011-12-17 Sebastien Bourdeauducqverilog: support for float parameters in instances
2011-12-16 Sebastien Bourdeauducqverilog: user-definable reset and clock
next