| 2019-08-21 | 
whitequark | back.pysim: allow coroutines as processes. | 
commit | commitdiff | tree | 
| 2019-08-20 | 
William D....  | test.test_examples: Convert pathlib-specific class...  | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | back.verilog: parse output of `yosys -V`. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | Fix nmigen.__version__ to work on git-archive artifacts. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | build.plat, hdl.ir: coordinate missing domain creation. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | vendor.lattice_ice40: use a local clock domain in creat...  | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | lib.cdc: use a local clock domain in ResetSynchronizer. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | README: fix typos. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | hdl.cd: implement local clock domains. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | back.pysim: index domains by identity, not by name. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | hdl.xfrm: lower resets in DomainLowerer as well. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | hdl.xfrm: consider fragment's own domains in DomainLowerer. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | formal→asserts | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | tracer: fix typo. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | build.plat: do not prepare fragments twice. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | back.{rtlil,verilog}: split convert_fragment() off...  | 
commit | commitdiff | tree | 
| 2019-08-18 | 
Robin Heinemann | build.dsl: add conn argument to Connector. | 
commit | commitdiff | tree | 
| 2019-08-18 | 
whitequark | compat.fhdl.decorators: avoid using deprecated NativeCE...  | 
commit | commitdiff | tree | 
| 2019-08-18 | 
whitequark | hdl.xfrm: make deprecated CEInserter more well-behaved. | 
commit | commitdiff | tree | 
| 2019-08-15 | 
whitequark | hdl.ast: implement Initial. | 
commit | commitdiff | tree | 
| 2019-08-15 | 
whitequark | hdl.xfrm: sample cache should be per-fragment. | 
commit | commitdiff | tree | 
| 2019-08-12 | 
whitequark | hdl.xfrm: CEInserter→EnableInserter. | 
commit | commitdiff | tree | 
| 2019-08-08 | 
whitequark | hdl.ast: hash-cons ValueKey. | 
commit | commitdiff | tree | 
| 2019-08-08 | 
whitequark | tracer: use sys._getframe directly. | 
commit | commitdiff | tree | 
| 2019-08-08 | 
whitequark | compat.fhdl.decorators: port from oMigen. | 
commit | commitdiff | tree | 
| 2019-08-08 | 
whitequark | compat.fhdl.module: fix finalization of transformed...  | 
commit | commitdiff | tree | 
| 2019-08-07 | 
whitequark | vendor.lattice_ice40: add iCE5LP2K support. | 
commit | commitdiff | tree | 
| 2019-08-07 | 
whitequark | vendor.lattice_ice40: add iCE40UP3K support. | 
commit | commitdiff | tree | 
| 2019-08-07 | 
whitequark | vendor.lattice_ice40: add iCE5LP1K support. | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_{spartan_3_6,7series}: reconsider default...  | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_spartan_3_6: reconsider bitgen defaults. | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_spartan_3_6: set bitgen defaults to ...  | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_spartan_3_6: always use -w for map/par...  | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_spartan_3_6: do not use retiming by default. | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_spartan_3_6: force use of bash on UNIX. | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | build.plat: allow selecting a specific UNIX shell inter...  | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.lattice_ice40: avoid routing conflicts with...  | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | back.rtlil: use a dummy wire, not 'x, when assigning...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | back.rtlil: actually match shape of left hand side. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | vendor.lattice_ice40: add missing signal indexing. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | build.run: use keyword-only arguments where appropriate. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | compat.fhdl.specials: track changes in build.plat. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.dsl: reword m.If(~True) warning to be more clear. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | build.plat,vendor: automatically create sync domain...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: allow adding more than one domain in missing...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: don't expose as ports missing domains added...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | build.plat: add default_rst, to be used with default_clk. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | build.plat: add default_clk{,_constraint,_frequency}. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: allow returning elaboratables from missing...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: raise DomainError if a domain is used but not...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: call back from Fragment.prepare if a clock...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.dsl: warn on suspicious statements like `m.If(...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | Improve test added in 29fee01f to not leak warnings. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | back.rtlil: fix sim-synth mismatch with assigns followi...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ast: fix typo. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ast: deprecate Value.part, add Value.{bit,word...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ast, back.rtlil: add source locations to anonymous...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: warn if .elaborate() returns None. | 
commit | commitdiff | tree | 
| 2019-07-31 | 
whitequark | hdl.xfrm: handle mem.{Read,Write}Port in CEInserter. | 
commit | commitdiff | tree | 
| 2019-07-21 | 
N. Engelhardt | vendor: don't emit duplicate iobuf submodule names. | 
commit | commitdiff | tree | 
| 2019-07-19 | 
N. Engelhardt | hdl.dsl: add getters to m.submodules. | 
commit | commitdiff | tree | 
| 2019-07-15 | 
Alain Péteut | lib.fifo: fix typo. | 
commit | commitdiff | tree | 
| 2019-07-14 | 
Staf Verhaegen | Pin: Add extra hierarchy level for name derivation | 
commit | commitdiff | tree | 
| 2019-07-14 | 
William D....  | build.run: Ensure batch script returns proper error...  | 
commit | commitdiff | tree | 
| 2019-07-12 | 
whitequark | back.pysim: correctly add gtkwave traces for signals...  | 
commit | commitdiff | tree | 
| 2019-07-10 | 
William D....  | build.dsl: Add optional name_suffix to Resource.family. | 
commit | commitdiff | tree | 
| 2019-07-10 | 
whitequark | back.pysim: avoid malformed VCD files when a decoder...  | 
commit | commitdiff | tree | 
| 2019-07-10 | 
whitequark | hdl.ir: make UnusedElaboratable a real warning. | 
commit | commitdiff | tree | 
| 2019-07-09 | 
whitequark | back.rtlil: add decodings to cases when switching on...  | 
commit | commitdiff | tree | 
| 2019-07-09 | 
whitequark | back.verilog: run proc_prune for much cleaner output. | 
commit | commitdiff | tree | 
| 2019-07-09 | 
whitequark | hdl.{ast,dsl},back.rtlil: track source locations for...  | 
commit | commitdiff | tree | 
| 2019-07-09 | 
Jacob Lifshay | tracer: add PyPy support to get_var_name(). | 
commit | commitdiff | tree | 
| 2019-07-09 | 
whitequark | build.dsl: add Resource.family abstraction. | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | build.{dsl,res}: allow platform-dependent attributes...  | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | hdl.rec: respect modifications to signals in Record...  | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | back.rtlil: don't name-prefix signals connected to...  | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | build.{dsl,res}: allow removing attributes from subsignals. | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | build.dsl: allow assertions on subsignal widths. | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | hdl.{ast,cd,dsl,xfrm}: reject inappropriately used...  | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | test: fix Travis. | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | test: generate examples to verilog as part of unit...  | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | examples/basic/ctr_ce: fix outdated syntax. | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | compat.genlib.fsm: fix after commit dac62754. | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | hdl.xfrm: don't overwrite source locations on ClockDoma...  | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | hdl.{dsl,mem,xfrm}: inject appropriate source locations. | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | back.rtlil: ignore empty source locations. | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | hdl.ast: use keyword-only arguments as appropriate. | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | back.rtlil: attach source locations to switches, not...  | 
commit | commitdiff | tree | 
| 2019-07-08 | 
whitequark | back.rtlil: use a more principled approach to attribute...  | 
commit | commitdiff | tree | 
| 2019-07-07 | 
Alain Péteut | vendor.xilinx_7series: generate also binary bitfile. | 
commit | commitdiff | tree | 
| 2019-07-07 | 
William D....  | vendor.xilinx_spartan_3_6: Add Spartan3A family support. | 
commit | commitdiff | tree | 
| 2019-07-07 | 
whitequark | vendor.lattice_ecp5: don't leave LUT inputs disconnected. | 
commit | commitdiff | tree | 
| 2019-07-07 | 
whitequark | hdl.dsl: further clarify error message for incorrect...  | 
commit | commitdiff | tree | 
| 2019-07-07 | 
whitequark | hdl.dsl: clarify error message for incorrect nesting. | 
commit | commitdiff | tree | 
| 2019-07-07 | 
whitequark | hdl.dsl: gracefully handle FSM with no states. | 
commit | commitdiff | tree | 
| 2019-07-07 | 
whitequark | build.plat: source a script with toolchain environment. | 
commit | commitdiff | tree | 
| 2019-07-07 | 
whitequark | build.run: only use os.path on the target OS. | 
commit | commitdiff | tree | 
| 2019-07-07 | 
whitequark | build.run: make BuildProducts abstract, add LocalBuildP...  | 
commit | commitdiff | tree | 
| 2019-07-06 | 
whitequark | build.plat, vendor.*: don't join strings passed as...  | 
commit | commitdiff | tree | 
| 2019-07-06 | 
whitequark | build.run: make sure BuildProducts._root is not easily...  | 
commit | commitdiff | tree | 
| next |