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yosys.git
2020-02-09
R. Ou
json: Change compat mode to directly emit ints <= 32...
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2020-02-07
Eddie Hung
Remove unnecessary comma
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2020-02-07
Eddie Hung
Merge pull request #1687 from YosysHQ/eddie/fix_ystests
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2020-02-07
Eddie Hung
techmap: fix shiftx2mux decomposition
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2020-02-07
Eddie Hung
Fix misc.abc9.abc9_abc9_luts
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2020-02-07
Marcin Kościelnicki
xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07
Marcin Kościelnicki
xilinx: Initial support for LUT4 devices.
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2020-02-07
Eddie Hung
Merge pull request #1685 from dh73/gowin
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2020-02-07
whitequark
Merge pull request #1683 from whitequark/write_verilog...
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2020-02-07
Marcin Kościelnicki
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07
Marcin Kościelnicki
xilinx: Add support for Spartan 3A DSP block RAMs.
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2020-02-06
Eddie Hung
Merge pull request #1684 from YosysHQ/eddie/xilinx_arit...
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2020-02-06
Diego H
Removing cells_sim.v from bram techmap pass
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2020-02-06
Eddie Hung
Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk
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2020-02-06
Eddie Hung
Fix/cleanup +/xilinx/arith_map.v
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2020-02-06
Marcin Kościelnicki
edif: more resilience to mismatched port connection...
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2020-02-06
whitequark
write_verilog: dump $mem cell attributes.
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2020-02-06
Eddie Hung
Merge pull request #1682 from YosysHQ/eddie/opt_after_t...
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2020-02-06
Eddie Hung
synth_*: call 'opt -fast' after 'techmap'
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2020-02-06
Eddie Hung
shiftx2mux: fix select out of bounds
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2020-02-05
Eddie Hung
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
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2020-02-05
Eddie Hung
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
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2020-02-05
Eddie Hung
abc9_ops: -reintegrate to use derived_type for box_ports
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2020-02-05
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2020-02-05
Eddie Hung
Merge pull request #1638 from YosysHQ/eddie/fix1631
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2020-02-05
Eddie Hung
Merge pull request #1661 from YosysHQ/eddie/abc9_required
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2020-02-03
Marcelina Kościelnicka
Add opt_lut_ins pass. (#1673)
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2020-02-02
David Shah
Merge pull request #1516 from YosysHQ/dave/dotstar
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2020-02-02
David Shah
Update CHANGELOG and README
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2020-02-02
David Shah
sv: Improve handling of wildcard port connections
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2020-02-02
David Shah
sv: More tests for wildcard port connections
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2020-02-02
David Shah
hierarchy: Correct handling of wildcard port connection...
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2020-02-02
David Shah
sv: Add tests for wildcard port connections
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2020-02-02
David Shah
hierarchy: Resolve SV wildcard port connections
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2020-02-02
David Shah
sv: Add lexing and parsing of .* (wildcard port conns)
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2020-02-02
David Shah
Merge pull request #1647 from YosysHQ/dave/sprintf
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2020-02-02
David Shah
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp...
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2020-02-02
Marcin Kościelnicki
xilinx: use RAM32M/RAM64M for memories with two read...
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2020-02-01
David Shah
xilinx_dsp: Add multonly scratchpad var to bypass
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2020-02-01
Marcin Kościelnicki
json: remove the 32-bit parameter special case
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2020-01-31
Eddie Hung
Merge pull request #1668 from gsomlo/gls-abc9-external
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2020-01-30
Gabriel Somlo
abc9: restore ability to use ABCEXTERNAL
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2020-01-30
Claire Wolf
Merge pull request #1667 from YosysHQ/clifford/verificnand
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2020-01-30
Claire Wolf
Merge pull request #1503 from YosysHQ/eddie/verific_help
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2020-01-30
Claire Wolf
Merge pull request #1654 from YosysHQ/eddie/sby_fix69
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2020-01-30
Claire Wolf
Add Verific support for OPER_REDUCE_NAND
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2020-01-29
Claire Wolf
Merge branch 'vector_fix' of https://github.com/Kmanfi...
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2020-01-29
Claire Wolf
Merge pull request #1662 from YosysHQ/dave/opt-reduce...
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2020-01-29
Claire Wolf
Merge pull request #1665 from YosysHQ/clifford/edifkeep
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2020-01-29
Claire Wolf
Merge pull request #1659 from YosysHQ/clifford/experimental
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2020-01-29
N. Engelhardt
Merge pull request #1510 from pumbor/master
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2020-01-29
Claire Wolf
Preserve wires with keep attribute in EDIF back-end
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2020-01-29
Miodrag Milanović
Merge pull request #1559 from YosysHQ/efinix_test_fix
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2020-01-29
Eddie Hung
Add "help -all" and "help -celltypes" sanity test
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2020-01-29
Eddie Hung
synth_xilinx: cleanup help
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2020-01-29
Eddie Hung
synth_xilinx: fix help when no active_design; fixes...
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2020-01-29
Marcin Kościelnicki
xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-28
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2020-01-28
Eddie Hung
Merge pull request #1660 from YosysHQ/eddie/abc9_unperm...
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2020-01-28
Eddie Hung
Add and use SigSpec::reverse()
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2020-01-28
Eddie Hung
Fix unresolved conflict from #1573
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2020-01-28
Miodrag Milanovic
Updated test to use assert-max
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2020-01-28
Claire Wolf
Improve logging use of experimental features
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2020-01-28
Claire Wolf
Merge pull request #1567 from YosysHQ/eddie/sat_init_wa...
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2020-01-28
N. Engelhardt
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
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2020-01-28
David Shah
opt_reduce: Call check() per run rather than per optimi...
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2020-01-28
Pepijn de Vos
redirect fuser stderr to /dev/null
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2020-01-28
Claire Wolf
Merge pull request #1553 from whitequark/manual-dffx
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2020-01-27
Eddie Hung
abc9_ops: -check for negative arrival/required times
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2020-01-27
Eddie Hung
Fix $lut input ordering -- SigSpec(std::initializer_lis...
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2020-01-27
Eddie Hung
Import tests from #1628
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2020-01-27
Eddie Hung
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
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2020-01-27
Eddie Hung
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
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2020-01-27
Eddie Hung
Fix typo
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2020-01-27
Eddie Hung
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
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2020-01-27
Eddie Hung
abc9_ops: add comments
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2020-01-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2020-01-27
Eddie Hung
verific: no help() when no YOSYS_ENABLE_VERIFIC
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2020-01-27
Eddie Hung
verific: also unflatten for 'hierarchy' flow as per...
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2020-01-27
Eddie Hung
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_...
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2020-01-27
Claire Wolf
Add log_experimental() and experimental() API and ...
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2020-01-27
Claire Wolf
Merge pull request #1658 from YosysHQ/clifford/smtbmcso...
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2020-01-27
Claire Wolf
Improve yosys-smtbmc "solver not found" handling
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2020-01-27
Claire Wolf
Merge pull request #1613 from porglezomp-misc/version...
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2020-01-24
Eddie Hung
read_aiger: set abc9_box_seq attr
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2020-01-24
Eddie Hung
ice40: add SB_SPRAM256KA arrival time
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2020-01-24
Eddie Hung
ice40: reduce ABC9 internal fanout warnings with a...
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2020-01-24
Eddie Hung
verific: unflatten struct ports
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2020-01-24
Eddie Hung
abc9: -reintegrate recover type from existing cell...
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2020-01-24
Eddie Hung
simple_abc9 tests to discard whitebox before write...
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2020-01-24
Eddie Hung
simple_abc9 tests to discard whitebox before write...
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2020-01-24
Eddie Hung
abc_box_id -> abc9_box_id in test
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2020-01-24
Eddie Hung
abc9: warning message if no modules selected
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2020-01-24
Eddie Hung
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
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2020-01-24
Eddie Hung
Test for (* keep *)-ed abc9_box_id
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2020-01-24
Eddie Hung
abc9_ops: -prep_xaiger to skip (* keep *) cells
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2020-01-24
Eddie Hung
abc_box_id -> abc9_box_id in test
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2020-01-23
Eddie Hung
abc9_ops -prep_dff: insert async s/r mux in holes when...
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2020-01-23
Eddie Hung
alumacc: undo accidental commit
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2020-01-22
Eddie Hung
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
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