| 2022-09-12 |
Dmitry Selyutin | power_insn: introduce pseudo cr_in2 |
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| 2022-09-12 |
Dmitry Selyutin | power_enums: strict selectors conversion |
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| 2022-09-12 |
Dmitry Selyutin | power_insn: fix typo |
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| 2022-09-12 |
Dmitry Selyutin | power_insn: support BRANCH and CR mode stubs |
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| 2022-09-12 |
Dmitry Selyutin | power_insn: refactor register operands |
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| 2022-09-12 |
Jacob Lifshay | add pseudocode for all fptrans ops |
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| 2022-09-12 |
Jacob Lifshay | add fptrans helpers, switching existing uses to new... |
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| 2022-09-12 |
Luke Kenneth... | add hphint and pack/unpack into SVSTATE SPR layout |
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| 2022-09-12 |
Jacob Lifshay | add fptrans ops to src/openpower/sv/trans/svp64.py |
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| 2022-09-12 |
Jacob Lifshay | add rest of new fptrans ops to CSVs |
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| 2022-09-12 |
Luke Kenneth... | remove pack/unpack - now part of sv.setvl |
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| 2022-09-12 |
Luke Kenneth... | add rudimentary sv.setvl unit test to just check that... |
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| 2022-09-12 |
Luke Kenneth... | add sv.setvl to instructions as a major hack |
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| 2022-09-12 |
Luke Kenneth... | split out setvl from sv.setvl test in test_pysvp64dis.py |
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| 2022-09-12 |
Luke Kenneth... | add extra tests "add." "addo" etc. to test_pysvp64dis.py |
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| 2022-09-12 |
Luke Kenneth... | demo that "setvl." is not reconstructed with Rc=1 mode |
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| 2022-09-12 |
Luke Kenneth... | some weird moving of opcodes around, probably because... |
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| 2022-09-12 |
Luke Kenneth... | skip addpcis for now, needs properly qualifying |
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| 2022-09-12 |
Jacob Lifshay | fix svanalysis failing due to missing comma in addpcis... |
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| 2022-09-11 |
Luke Kenneth... | add new CRIn2Sel for later, for getting rid of CRInSel... |
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| 2022-09-11 |
Luke Kenneth... | BFT does not exist |
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| 2022-09-11 |
Luke Kenneth... | add sv.isel 12,2,3,*99 test to test_pysvp64dis.py |
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| 2022-09-11 |
Luke Kenneth... | add some CR3 pysvp64dis.py tests, sv.crand |
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| 2022-09-11 |
Dmitry Selyutin | power_insn: check exact matches directly in set |
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| 2022-09-11 |
Dmitry Selyutin | power_insn: group opcodes and names |
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| 2022-09-11 |
Luke Kenneth... | add sv.isel asm-disasm tests to test_pysvp64dis.py |
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| 2022-09-11 |
Luke Kenneth... | add missing addpcis to power_enums.py and minor_19.csv |
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| 2022-09-11 |
Luke Kenneth... | convert minor_19 to bitpattern (for adding addpcis) |
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| 2022-09-11 |
Luke Kenneth... | whoops lsbshf=2 for CR5 |
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| 2022-09-11 |
Luke Kenneth... | whoops missed lsb-shift parameter |
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| 2022-09-11 |
Luke Kenneth... | add comments into CR5Operand class |
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| 2022-09-11 |
Luke Kenneth... | add CR5Operand and CR3Operand to power_insns.py |
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| 2022-09-10 |
Luke Kenneth... | huhn? addpcis converts to .long? huhn? |
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| 2022-09-10 |
Luke Kenneth... | fix issue with pysvp64dis.py load() reading from stdin |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: perform minor opcodes cleanup |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: hopefully final take on the opcodes |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: yet another take on the opcodes |
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| 2022-09-10 |
Luke Kenneth... | whitespace cleanup |
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| 2022-09-10 |
Luke Kenneth... | add quine-mckluskey algorithm |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: refactor register verbose assembly |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: support pcode |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: tune TargetAddrOperand disassembly |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: support CR remap |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: support non-zero operands |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: simplify operand naming conventions |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: drop redundant dataclass incantations |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: do not print blob suffix unless needed |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: do not panic upon database query |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: refactor opcode matching |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: support D operand in DX form |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: refactor span detection |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: simplify code |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: remove redundant code |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: decouple extra merge routine |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: rename extra to spec |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: deprecate redundant else section |
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| 2022-09-10 |
Dmitry Selyutin | power_insn: rename Extra classes |
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| 2022-09-10 |
Dmitry Selyutin | fields.text: this fish ain't moving |
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| 2022-09-10 |
Jacob Lifshay | reallocate fcbrt(s) to match new fptrans allocations |
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| 2022-09-10 |
Jacob Lifshay | move ffadds to not conflict with fptrans -- makes space... |
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| 2022-09-09 |
Luke Kenneth... | add fishmv fmvis addpcis instructions to test_pysvp64dis.py |
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| 2022-09-09 |
Luke Kenneth... | add subtests |
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| 2022-09-09 |
Luke Kenneth... | hooray got test_pysvp64dis.py working with new Verbosit... |
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| 2022-09-09 |
Dmitry Selyutin | power_insn: support verbosity levels |
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| 2022-09-09 |
Dmitry Selyutin | power_insn: indent refactoring |
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| 2022-09-09 |
Luke Kenneth... | add seek/tell on load in pysvp64dis so that generator... |
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| 2022-09-09 |
Luke Kenneth... | add "short" argument (TODO pick better name) to pysvp64dis |
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| 2022-09-09 |
Luke Kenneth... | add pysvp64dis tester |
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| 2022-09-09 |
Luke Kenneth... | extend short down into rest of disassembly |
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| 2022-09-09 |
Luke Kenneth... | add "short" form of instruction - not output hex-encoding |
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| 2022-09-09 |
Luke Kenneth... | "D" of fishmv RT,D has to be done as a custom field |
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| 2022-09-09 |
Dmitry Selyutin | fields.text: this fish ain't moving |
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| 2022-09-09 |
Dmitry Selyutin | minor_22: make svshape2 really shaped |
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| 2022-09-09 |
Dmitry Selyutin | minor_31: fix setb form |
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| 2022-09-09 |
Dmitry Selyutin | minor_30: fix rldicl form |
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| 2022-09-09 |
Luke Kenneth... | add default arg byteorder=LITTLE to pysvp64dis |
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| 2022-09-09 |
Luke Kenneth... | added missing RA RB RT to TLI-Form fields.txt |
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| 2022-09-09 |
Dmitry Selyutin | major: fix andi./andis. form |
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| 2022-09-09 |
Dmitry Selyutin | minor_30: fix rldcl/rldcr forms |
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| 2022-09-08 |
Luke Kenneth... | whitespace |
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| 2022-09-08 |
Dmitry Selyutin | pysvp64asm: fix missing arguments |
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| 2022-09-08 |
Luke Kenneth... | rename svshape and svoffset fields |
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| 2022-09-08 |
Dmitry Selyutin | svshape2: rename fields |
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| 2022-09-07 |
Dmitry Selyutin | power_insn: dump operand type (scalar/vector) |
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| 2022-09-07 |
Luke Kenneth... | add fcpsgn parallel reduction test |
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| 2022-09-07 |
Luke Kenneth... | whoops forgot to strip "NN/NN=insn" in power_svp64.py |
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| 2022-09-07 |
Luke Kenneth... | add 2nd parallel prefix test, this time subtract (non... |
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| 2022-09-07 |
Dmitry Selyutin | power_insn: fix immediate operands |
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| 2022-09-07 |
Dmitry Selyutin | power_insn: refactor operands disassembly |
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| 2022-09-07 |
Dmitry Selyutin | power_fields: deprecate arrays |
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| 2022-09-07 |
Dmitry Selyutin | power_insn: support EXTRA2/EXTRA3 GPR/FPR |
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| 2022-09-06 |
Dmitry Selyutin | power_fields: allow getting individual field bits |
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| 2022-09-06 |
Dmitry Selyutin | power_insn: use tuple for bit ranges in fields |
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| 2022-09-06 |
Dmitry Selyutin | pysvp64asm: create database once |
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| 2022-09-06 |
Dmitry Selyutin | power_insn: fix naming conventions |
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| 2022-09-06 |
Dmitry Selyutin | power_insn: stricter reg type check |
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| 2022-09-06 |
Luke Kenneth... | add first functional confirmed unit test for parallel... |
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| 2022-09-06 |
Luke Kenneth... | REMAP parallel-reduce: |
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| 2022-09-06 |
Jacob Lifshay | add fixedsync.py to .gitignore |
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| 2022-09-06 |
Jacob Lifshay | fix incorrect comment |
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