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yosys.git
2019-05-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/opt_rmdff...
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2019-05-23
Eddie Hung
Merge pull request #1036 from YosysHQ/eddie/xilinx_dram
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2019-05-23
Eddie Hung
Fix spacing
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2019-05-23
Eddie Hung
Add "min bits" and "min wports" to xilinx dram rules
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2019-05-23
Eddie Hung
Add opt_rmdff tests
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2019-05-23
Eddie Hung
opt_rmdff to work on $dffe and $_DFFE_*
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2019-05-23
Eddie Hung
Add whitebox support to DRAM
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2019-05-23
Stefan Biereigel
fix assignment of non-wires
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2019-05-23
Stefan Biereigel
add simple test case for wand/wor
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2019-05-23
Stefan Biereigel
fix indentation across files
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2019-05-23
Stefan Biereigel
implementation for assignments working
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2019-05-23
Stefan Biereigel
make lexer/parser aware of wand/wor net types
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2019-05-23
Clifford Wolf
Merge pull request #1031 from mdaiter/optimizeLookupTab...
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2019-05-22
Matthew Daiter
Optimize numberOfPermutations
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2019-05-22
Kaj Tuomi
OS X related fixes.
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2019-05-22
Clifford Wolf
Keep zero-width wires in opt_clean if and only if they...
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2019-05-22
Clifford Wolf
Fix handling of warning and error messages within log_m...
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2019-05-22
Clifford Wolf
Merge pull request #1019 from YosysHQ/clifford/fix1016
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2019-05-22
Clifford Wolf
Merge pull request #1021 from ucb-bar/fixfirrtl_shr,neg
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2019-05-22
Eddie Hung
shift register inference before mux
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2019-05-22
Eddie Hung
Fix/workaround symptom unveiled by #1023
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2019-05-22
Eddie Hung
Merge pull request #1024 from YosysHQ/eddie/fix_Wmissin...
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2019-05-22
Eddie Hung
Rename label
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2019-05-22
Eddie Hung
Try again
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2019-05-21
Eddie Hung
Fix warning
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2019-05-21
Eddie Hung
Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21
Eddie Hung
Pad all boxes so that all input/output connections...
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2019-05-21
Eddie Hung
Modify LUT area cost to be same as old abc
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2019-05-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-21
Jim Lawson
Fix static shift operands, neg result type, minor forma...
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2019-05-21
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-05-20
Clifford Wolf
Add "wreduce -keepdc", fixes #1016
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2019-05-18
Clifford Wolf
Merge pull request #1017 from Kmanfi/bigger_verilog_files
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2019-05-18
Kaj Tuomi
Read bigger Verilog files.
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2019-05-16
Clifford Wolf
Merge pull request #1013 from antmicro/parameter_attributes
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2019-05-16
Maciej Kurc
Added tests for Verilog frontent for attributes on...
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2019-05-16
Maciej Kurc
Added support for parsing attributes on parameters...
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2019-05-15
Clifford Wolf
Merge pull request #1012 from YosysHQ/clifford/sigspecrw
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2019-05-15
Clifford Wolf
Improvements in opt_clean
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2019-05-15
Clifford Wolf
Add rewrite_sigspecs2, Improve remove() wires
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2019-05-15
Clifford Wolf
Do not leak file descriptors in cover.cc
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2019-05-15
Clifford Wolf
Merge pull request #1011 from hzeller/fix-constructing...
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2019-05-15
Clifford Wolf
Merge pull request #1010 from hzeller/yacc-self-contained
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2019-05-15
Clifford Wolf
Merge pull request #1008 from thasti/fix_libyosys_build
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2019-05-15
David Shah
Merge pull request #1005 from smunaut/ice40_hfosc_trim
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2019-05-15
Henner Zeller
Fix two instances of integer-assignment to string.
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2019-05-15
Henner Zeller
Make the generated *.tab.hh include all the headers...
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2019-05-14
Stefan Biereigel
extract python prefix to allow overriding
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2019-05-14
Stefan Biereigel
remove ldconfig call
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2019-05-14
Stefan Biereigel
add mkdir for libyosys target, explicitly copy to targe...
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2019-05-14
whitequark
bugpoint: check for -script option.
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2019-05-13
Sylvain Munaut
ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
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2019-05-12
Clifford Wolf
Merge pull request #1004 from YosysHQ/clifford/fix1002
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2019-05-12
Clifford Wolf
Fix handling of glob_abort_cnt in opt_muxtree, fixes...
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2019-05-11
Clifford Wolf
Merge pull request #1003 from makaimann/zinit-all
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2019-05-11
Clifford Wolf
Add "fmcombine -initeq -anyeq"
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2019-05-11
Clifford Wolf
Add "stat -tech xilinx"
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2019-05-10
Makai Mann
Zinit option '-singleton' -> '-all'
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2019-05-09
Clifford Wolf
Merge pull request #1000 from bwidawsk/synth-format
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2019-05-09
Ben Widawsky
Fix formatting for synth_intel.cc
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2019-05-09
Ben Widawsky
Add a .clang-format
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2019-05-09
Clifford Wolf
Add $stop to documentation
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2019-05-08
Clifford Wolf
Remove added newline (by re-running minisat 00_UPDATE.sh)
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2019-05-08
Clifford Wolf
Merge pull request #991 from kristofferkoch/gcc9-warnings
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2019-05-08
Kristoffer...
Fix all warnings that occurred when compiling with...
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2019-05-08
Clifford Wolf
Merge pull request #998 from mdaiter/get_bool_attribute...
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2019-05-08
Matthew Daiter
Minor optimization to get_attribute_bool
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2019-05-07
Clifford Wolf
Add test case from #997
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2019-05-07
Clifford Wolf
Fix handling of partial init attributes in write_verilo...
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2019-05-07
Clifford Wolf
Merge pull request #996 from mdaiter/ceil_log2_opts
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2019-05-07
Matthew Daiter
Optimize ceil_log2 function
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2019-05-07
Clifford Wolf
Add "synth_xilinx -arch"
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2019-05-07
Clifford Wolf
More opt_clean cleanups
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2019-05-06
Clifford Wolf
Merge pull request #946 from YosysHQ/clifford/specify
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2019-05-06
Clifford Wolf
Merge pull request #975 from YosysHQ/clifford/fix968
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2019-05-06
Clifford Wolf
Merge pull request #871 from YosysHQ/verific_import
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2019-05-06
Clifford Wolf
Add tests/various/chparam.sh
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2019-05-06
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-05-06
Clifford Wolf
Fix the other bison warning in ilang_parser.y
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2019-05-06
Clifford Wolf
Bugfix in peepopt_shiftmul.pmg
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2019-05-06
Clifford Wolf
Merge pull request #992 from bwidawsk/bison-fix
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2019-05-06
Clifford Wolf
Merge pull request #989 from YosysHQ/dave/abc_name_improve
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2019-05-06
Clifford Wolf
Fix bug in "expose -input"
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2019-05-06
Clifford Wolf
Cleanups in opt_clean
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2019-05-06
Clifford Wolf
Improve tests/various/specify.ys
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2019-05-06
Clifford Wolf
Add "real" keyword to ilang format
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2019-05-06
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-05-06
Ben Widawsky
verilog_parser: Fix Bison warning
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2019-05-04
Clifford Wolf
Merge pull request #988 from YosysHQ/clifford/fix987
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2019-05-04
David Shah
abc: Fix handling of postfixed names (e.g. for retiming)
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2019-05-04
David Shah
abc: Improve name recovery
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2019-05-04
Clifford Wolf
Improve opt_clean handling of unused wires
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2019-05-04
Clifford Wolf
Add support for SVA "final" keyword
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2019-05-04
Clifford Wolf
Improve write_verilog specify support
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2019-05-04
Clifford Wolf
Update README
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2019-05-04
Clifford Wolf
Add approximate support for SV "var" keyword, fixes...
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2019-05-03
Eddie Hung
More testing
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2019-05-03
Eddie Hung
Fix spacing
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2019-05-03
Eddie Hung
Add quick-and-dirty specify tests
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