gem5.git
2019-04-19 Daniel R. Carvalhomem: Allow packet to provide its own addr range
2019-04-16 Andrea Mondellimem: missing override specifier
2019-04-14 Gabe Blackmem: Teach SimpleMem to return a MemBackdoor when appro...
2019-04-14 Gabe Blackmem: Maintain a back door into the AbstractMem's backin...
2019-04-12 Rutuja Ozatests: Add tests for learning_gem5 configs
2019-04-12 Jason Lowe... tests: Add protocol as an option to SconsFixture
2019-04-12 Hoa Nguyentests: add riscv to cpu tests
2019-04-11 Anis Peysieuxmem-cache: Fix RRPV for RRIP
2019-04-11 Giacomo Travagliniarch-arm: Enable PMSELR_EL0 read in PMU
2019-04-10 Gabe Blackmem: Plumb backdoor requests through the xbar classes.
2019-04-10 Gabe Blacksystemc: Teach the TLM bridges how to use gem5's new...
2019-04-10 Gabe Blackmem: Add sendAtomicBackdoor/recvAtomicBackdoor port...
2019-04-10 Nikos Nikolerismem-cache: Fix MSHR handling of cache clean requests
2019-04-10 Giacomo Travaglinicpu: O3 switchFreeList checking VecElems instead of...
2019-04-08 Jason Lowe... learning_gem5,configs: Update ruby_test
2019-04-08 Jason Lowe... learning_gem5: Fix vector port panic in SimpleCache
2019-04-08 Jason Lowe... configs: Fix import path error in learning_gem5 part3
2019-04-08 Jason Lowe... configs: Add full path for learning_gem5 binaries
2019-04-08 Ryan Gambordconfigs: Removed redudant exec-style import
2019-04-06 Gabe Blackmem: Add a MemBackdoor type to track memory backdoors.
2019-04-05 Nikos Nikoleriscpu: Correctly account for executed instructions in...
2019-04-05 Ryan Gambordmem-cache: ambiguous use of abs function
2019-04-05 Jason Lowe... mem: Reverse order of write/read mem queue check
2019-04-05 Jason Lowe... tests: Add Jenkins presubmit and continuous test scripts
2019-04-04 Javier Buenomem-cache: AMPM Prefetcher fails when restoring from...
2019-04-03 Andrea Mondellimisc: Removed inconsistency in O3* debug msgs
2019-04-03 Andrea Mondelliarch-mips: added missing override specifier (o3)
2019-04-03 Javier Buenomem-cache: Fix PIF prefetcher compilation error with...
2019-04-03 Javier Buenomem-cache: ISB prefetcher was triggering an assertion
2019-04-03 Javier Buenomem-cache: Fix panic in Indirect Memory prefetcher
2019-04-02 Giacomo Travaglinidev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
2019-04-02 Ivan Pizarromem-cache: Proactive Instruction Fetch Implementation
2019-04-01 Andrea Mondellidev-arm: Correct cast of template parameter
2019-03-29 Gabe Blacksystemc: Templatize the gem5/TLM bridge SimObjects.
2019-03-29 Gabe Blacksystemc: Delete extra code from src/systemc/tlm_bridge.
2019-03-29 Gabe Blacksystemc: Create unified gem5/TLM bridge SimObjects.
2019-03-29 Gabe Blacktlm: Initial import of tlm/gem5 bridge code.
2019-03-29 Gabe Blacksystemc: Provide a utility Port TLM socket wrapper...
2019-03-28 Javier Buenocpu: Added a probe to notify the address of retired...
2019-03-28 Daniel R. Carvalhomem-cache: Remove extra cache header from AMAP
2019-03-28 Javier Setoainarch-arm: Fix use of bitwise operators on booleans
2019-03-28 Giacomo Travagliniarch-arm: Fix index generation for VecElem operands
2019-03-27 Giacomo Travaglinidev-arm: Rename GIC maintenance interrupt from ppint...
2019-03-27 Giacomo Travaglinidev-arm: Fix GICv3 overflow for INTID > 256
2019-03-27 Giacomo Travaglinidev-arm: Writing ICENABLER for non-SPIs is RAZ/WI ...
2019-03-27 Javier Buenoconfig: Use the corresponding HPI Caches when using...
2019-03-27 Pau Cabrecpu: Fixed the indirect branch predictor GHR handling
2019-03-26 Gabe Blackmem: Deleting this init() method was accidentally dropp...
2019-03-26 Gabe Blackmem: Clean up the xbars a little.
2019-03-26 Gabe Blackbase: Make AddrRangeMap able to return non-const iterators.
2019-03-26 Javier Buenoconfigs: fix class reference in CacheConfigs
2019-03-26 Giacomo Travaglinidev-arm: Set/Unset dma coherent mode from python
2019-03-26 Isaac Sánchez... base,python: Fix to allow multiple --debug-ignore values.
2019-03-25 Daniel R. Carvalhoconfigs: Remove default kernel value from system creation
2019-03-25 Javier Setoainarch-arm: Add missing fall-through defaults
2019-03-25 Sandipan Dasarch-power: Rename program counter registers
2019-03-25 Sandipan Dasarch-power: Simplify doubleword operand types
2019-03-23 Andrea Mondellimisc: missing override specifier
2019-03-22 Tiago Mucksim-se: Fixed initialization array size
2019-03-22 Giacomo Travaglinibase: Fix CircularQueue's operator-= when negative...
2019-03-22 Giacomo Travaglinibase: Fix CircularQueue when diffing iterators
2019-03-21 Andrea Mondellidev-arm: ambiguous use of getPort()
2019-03-21 Jason Lowe... tests: Add ignore for stdin not terminal
2019-03-21 Jason Lowe... tests: Use full path for DownloadedProgram
2019-03-21 Jason Lowe... tests: Fix race condition in download fixture
2019-03-21 Jason Lowe... ext,tests: Add back failing exceptions
2019-03-21 Jason Lowe... tests,ext: Add skip_cleanup implementation for TempdirF...
2019-03-21 Jason Lowe... ext,tests: Make return code based on test results
2019-03-21 Jason Lowe... ext,test: Provide default terminal size
2019-03-21 Ryan Gambordcpu-kvm: Added informative error message
2019-03-20 Javier Buenomem-cache: Added the STeMS prefetcher
2019-03-19 Gabe Blacksystemc: Hook up gem5_getPort to the gem5 getPort mecha...
2019-03-19 Gabe Blackarch, cpu, dev, gpu, mem, sim, python: start using...
2019-03-19 Gabe Blackpython: Switch to the new getPort mechanism to connect...
2019-03-19 Gabe Blackmem: Move bind() and unbind() into the Port class.
2019-03-19 Gabe Blacksim: Add a getPort function to SimObject.
2019-03-19 Ryan Gambordutil: Build m5 with -no-pie flag
2019-03-18 Gabe Blackpython: Change || to && for MessageBuffers in connectPorts.
2019-03-18 Gabe Blackpython: Improve how templated SimObject classes are...
2019-03-18 Hoa Nguyenscons: fix disable_partial logic for fast binary
2019-03-18 Ryan Gambordutil: changed shebang on gem5img.py to python2.7
2019-03-18 Andrea Mondellimem-cache: tautological comparison of byteOrder
2019-03-18 Andreas Sandbergconfigs: Use absolute import paths
2019-03-15 Ryan Gambordmem: Removed circular include ref
2019-03-15 Javier Buenomem-cache: Added the Indirect Memory Prefetcher
2019-03-15 Gabe Blackmem: Move the Port base class into sim.
2019-03-15 Gabe Blackdev: Make EtherInt inherit from Port.
2019-03-15 Gabe Blackmem: Track the MemObject owner in MasterPort and SlavePort.
2019-03-15 Gabe Blackpython: Simplify connectPorts() around EtherObject...
2019-03-15 Gabe Blackdev: Make the EtherDevice class inherit EtherObject.
2019-03-15 Gabe Blackdev: Turn EtherObject into an interface class.
2019-03-15 Danielmem-cache: Fix write hit latency calculation order
2019-03-14 Gabe Blackpython: Teach cxxMethod how to set return_value_policy.
2019-03-14 Gabe Blackpython: Teach PyBindMethod how to set return_value_policy.
2019-03-14 Andrea Mondellicpu: Refactor of Physical Register implementation
2019-03-14 Daniel R. Carvalhopython: Fix unknown params and proxy multiplication
2019-03-14 Jairo Balartdev-arm: cleanup of gicv3 CPU interface code and fixes
2019-03-14 Giacomo Gabrielliarch-arm,cpu: Add initial support for Arm SVE
2019-03-12 Gabe Blackscons: Don't use isdir in AddLocalRPATH.
2019-03-12 Daniel R. Carvalhosim: Add size to array unserialization error message
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