yosys.git
2019-08-22 Eddie HungForgot to set ud_variable.minlen
2019-08-22 Eddie HungDo not run xilinx_srl_pm in fixed loop
2019-08-22 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-22 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-22 Eddie HungMerge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
2019-08-22 Clifford WolfBump year in copyright notice
2019-08-22 Clifford WolfFix missing newline at end of file
2019-08-22 Clifford WolfMerge pull request #1289 from mmicko/anlogic_fixes
2019-08-22 Clifford WolfFix missing newline at end of file
2019-08-22 Clifford WolfMerge pull request #1281 from mmicko/efinix
2019-08-22 Eddie HungCopy-paste typo
2019-08-22 Eddie HungRespect opt_expr -keepdc as per @cliffordwolf
2019-08-22 Eddie HungHandle $shift and Y_WIDTH > 1 as per @cliffordwolf
2019-08-22 Eddie HungAdd cover()
2019-08-22 Eddie HungCanonical form
2019-08-22 Clifford WolfMerge pull request #1316 from YosysHQ/eddie/fix_mem2reg
2019-08-22 Eddie HungAdd test
2019-08-22 Eddie Hungopt_expr to trim A port of $shiftx if Y_WIDTH == 1
2019-08-22 Eddie HungReuse var
2019-08-22 Eddie HungRevert "Trim shiftx_width when upper bits are 1'bx"
2019-08-22 Eddie Hungopt_expr to trim A port of $shiftx if Y_WIDTH == 1
2019-08-22 Eddie HungTrim shiftx_width when upper bits are 1'bx
2019-08-22 Eddie HungAdd comment
2019-08-22 Eddie HungAdd variable length support to xilinx_srl
2019-08-21 Eddie HungRename pattern to fixed
2019-08-21 Eddie Hungattribute -> attr
2019-08-21 Eddie HungUse Cell::has_keep_attribute()
2019-08-21 Eddie Hungabc9 to perform new 'map_ffs' before 'map_luts'
2019-08-21 Eddie Hungxilinx_srl to support FDRE and FDRE_1
2019-08-21 Eddie HungFix polarity of EN_POL
2019-08-21 whitequarkMerge pull request #1315 from mmicko/fix_dependencies
2019-08-21 Eddie HungAdd CLKPOL == 0
2019-08-21 Eddie HungReject if not minlen from inside pattern matcher
2019-08-21 Eddie HungGet wire via SigBit
2019-08-21 Eddie HungRespect \keep on cells or wires
2019-08-21 Eddie HungMerge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl
2019-08-21 Eddie Hungmem2reg to preserve user attributes and src
2019-08-21 Eddie HungAdd init support
2019-08-21 Eddie HungFix spacing
2019-08-21 Eddie HungInitial progress on xilinx_srl
2019-08-21 Miodrag MilanovicFix test_pmgen deps
2019-08-21 Clifford WolfMerge pull request #1314 from YosysHQ/eddie/fix_techmap
2019-08-21 Eddie HungMissing newline
2019-08-21 Eddie HungFix copy-paste typo
2019-08-21 Eddie HungGrammar
2019-08-21 Eddie HungAdd test
2019-08-21 Eddie Hungtechmap -max_iter to apply to each module individually
2019-08-20 Eddie HungMerge pull request #1209 from YosysHQ/eddie/synth_xilinx
2019-08-20 Eddie HungMerge pull request #1304 from YosysHQ/eddie/abc9_refactor
2019-08-20 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-20 Clifford WolfMerge pull request #1298 from YosysHQ/clifford/pmgen
2019-08-20 Clifford WolfMerge branch 'master' into clifford/pmgen
2019-08-20 Clifford WolfAdd test case for real parameters
2019-08-20 Clifford WolfMerge pull request #1308 from jakobwenzel/real_params
2019-08-20 whitequarkMerge pull request #1309 from whitequark/proc_clean...
2019-08-19 Eddie HungFix typo
2019-08-19 Eddie HungFix typo
2019-08-19 Eddie HungID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc
2019-08-19 Eddie HungClarify with 'only'
2019-08-19 Eddie HungUpdate doc
2019-08-19 Eddie HungUnify abc_carry_{in,out} into abc_carry and use port...
2019-08-19 whitequarkproc_clean: fix order of switch insertion.
2019-08-19 Jakob Wenzelhandle real values when deriving ast modules
2019-08-19 Clifford WolfMerge pull request #1306 from mmicko/gitignore_fix
2019-08-19 Clifford WolfAdd *.sv to tests/simple_abc9/.gitignore
2019-08-19 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-08-19 Clifford WolfMerge pull request #1305 from YosysHQ/clifford/testfast
2019-08-19 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-08-19 Eddie HungRemoval of more `stat` calls from tests
2019-08-18 Miodrag MilanovicMerge remote-tracking branch 'upstream/master' into...
2019-08-18 Miodrag MilanovicIgnore all generated headers for pmgen pass
2019-08-18 whitequarkMerge pull request #1290 from YosysHQ/eddie/pr1266_again
2019-08-18 whitequarkMerge branch 'master' into eddie/pr1266_again
2019-08-17 Clifford WolfMerge pull request #1283 from YosysHQ/clifford/fix1255
2019-08-17 Clifford WolfMerge pull request #1303 from YosysHQ/bogdanvuk/opt_share
2019-08-17 Clifford WolfMerge pull request #1300 from YosysHQ/eddie/cleanup2
2019-08-17 Clifford WolfFix erroneous ifndef-NDEBUG in verific.cc
2019-08-17 Clifford WolfSpeed up "make test" and related cleanups
2019-08-17 Clifford WolfAdd test for pmtest_test "reduce" demo pattern
2019-08-17 Clifford WolfRefactor pmgen rollback mechanism
2019-08-17 Clifford WolfImprovements in "test_pmgen -generate"
2019-08-17 Clifford WolfAdd pmgen "fallthrough" statement
2019-08-16 Eddie HungUse ID()
2019-08-16 Eddie HungAdd doc for abc_* attributes
2019-08-16 Eddie HungUpdate abc_* attr in ecp5 and ice40
2019-08-16 Eddie HungCompute abc_scc_break and move CI/CO outside of each...
2019-08-16 Eddie HungAttach abc_scc_break, abc_carry_{in,out} attr to ports...
2019-08-16 Eddie HungMerge pull request #1250 from bwidawsk/master
2019-08-16 Eddie HungUse ID() macro
2019-08-16 Eddie HungAdd 'opt_share' to CHANGELOG
2019-08-16 Eddie HungAdd 'opt_share' to 'opt -full'
2019-08-16 Eddie HungMerge https://github.com/bogdanvuk/yosys into bogdanvuk...
2019-08-16 Eddie HungRemove unused variable
2019-08-16 Eddie HungAdd help() call
2019-08-16 Eddie HungMove namespace alias
2019-08-16 Eddie HungRemove `using namespace RTLIL;`
2019-08-16 Clifford WolfMinor bugfix in "test_pmgen -generate"
2019-08-16 Clifford WolfMerge pull request #1302 from mmicko/dfflibmap_regression
2019-08-16 Clifford WolfDo not use Verific in tests/various/write_gzip.ys
2019-08-16 Clifford WolfAdd pmgen finish statement, return number of matches
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