2019-07-18 |
Eddie Hung | mul2dsp to create cells that can be interchanged with... |
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2019-07-18 |
Eddie Hung | Check if RHS is empty first |
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2019-07-18 |
Eddie Hung | Make consistent |
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2019-07-18 |
Eddie Hung | Do not autoremove ffP aor muxP |
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2019-07-18 |
Eddie Hung | Improve pattern matcher to match subsets of $dffe?... |
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2019-07-18 |
Eddie Hung | Improve A/B reg packing |
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2019-07-18 |
Eddie Hung | Do not autoremove A/B registers since they might have... |
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2019-07-18 |
Eddie Hung | Fix xilinx_dsp index cast |
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2019-07-18 |
Eddie Hung | Fix signed multiplier decomposition |
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2019-07-18 |
Eddie Hung | Use single DSP_SIGNEDONLY macro |
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2019-07-18 |
Eddie Hung | Working for unsigned |
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2019-07-18 |
Eddie Hung | Cleanup |
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2019-07-18 |
Eddie Hung | Wrong wildcard symbol |
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2019-07-18 |
Eddie Hung | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into... |
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2019-07-18 |
David Shah | mul2dsp: Lower partial products always have unsigned... |
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2019-07-17 |
Eddie Hung | Make all operands signed |
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2019-07-17 |
Eddie Hung | Update comment |
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2019-07-17 |
Eddie Hung | Pattern matcher to check pool of bits, not exactly |
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2019-07-17 |
Eddie Hung | Fix mul2dsp signedness |
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2019-07-17 |
Eddie Hung | A_SIGNED == B_SIGNED so flip both |
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2019-07-17 |
Eddie Hung | SigSpec::remove_const() to return SigSpec& |
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2019-07-16 |
Eddie Hung | Add DSP_{A,B}_SIGNEDONLY macro |
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2019-07-16 |
Eddie Hung | Signedness |
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2019-07-16 |
Eddie Hung | Signed extension |
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2019-07-16 |
Eddie Hung | Revert drop down to 24x16 multipliers for all |
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2019-07-16 |
Eddie Hung | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into... |
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2019-07-16 |
Eddie Hung | Add support {A,B,P}REG packing |
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2019-07-16 |
Eddie Hung | SigSpec::extract to allow negative length |
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2019-07-16 |
Eddie Hung | Add support for {A,B,P}REG in DSP48E1 |
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2019-07-16 |
David Shah | xilinx: Add correct signed behaviour to DSP48E1 model |
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2019-07-16 |
David Shah | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual... |
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2019-07-16 |
David Shah | mul2dsp: Fix edge case where Y_WIDTH is less than B_WID... |
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2019-07-16 |
David Shah | mul2dsp: Fix indentation |
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2019-07-15 |
Eddie Hung | Do not swap if equals |
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2019-07-15 |
Eddie Hung | SigSpec::extend_u0() to return *this |
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2019-07-15 |
Eddie Hung | Oops forgot these files |
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2019-07-15 |
Eddie Hung | Add xilinx_dsp for register packing |
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2019-07-15 |
Eddie Hung | OUT port to Y in generic DSP |
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2019-07-15 |
Eddie Hung | Move DSP mapping back out to dsp_map.v |
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2019-07-15 |
Eddie Hung | Only swap if B_WIDTH > A_WIDTH |
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2019-07-15 |
Eddie Hung | Tidy up |
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2019-07-15 |
Eddie Hung | Move DSP48E1 model out of cells_xtra, initial multiply... |
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2019-07-15 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xc7dsp |
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2019-07-14 |
Eddie Hung | Merge pull request #1194 from cr1901/miss-semi |
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2019-07-14 |
William D.... | Fix missing semicolon in Windows-specific code in aiger... |
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2019-07-12 |
Clifford Wolf | Merge pull request #1183 from whitequark/ice40-always... |
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2019-07-11 |
whitequark | synth_ice40: switch -relut to be always on. |
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2019-07-11 |
whitequark | synth_ice40: fix help text typo. NFC. |
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2019-07-11 |
Eddie Hung | Merge pull request #1182 from koriakin/xc6s-bram |
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2019-07-11 |
Eddie Hung | Merge pull request #1185 from koriakin/xc-ff-init-vals |
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2019-07-11 |
Marcin Kościelnicki | xilinx: Fix the default values for FDPE/FDSE INIT attri... |
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2019-07-11 |
Eddie Hung | Enable &mfs for abc9, even if it only currently works... |
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2019-07-11 |
Marcin Kościelnicki | synth_xilinx: Initial Spartan 6 block RAM inference... |
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2019-07-11 |
Clifford Wolf | Merge pull request #1172 from whitequark/write_verilog... |
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2019-07-11 |
Clifford Wolf | Merge pull request #1179 from whitequark/attrmap-proc |
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2019-07-10 |
Eddie Hung | Move dsp_map.v into cells_map.v; cleanup synth_xilinx... |
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2019-07-10 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xc7dsp |
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2019-07-10 |
Eddie Hung | Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime |
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2019-07-10 |
Eddie Hung | Merge pull request #1148 from YosysHQ/xc7mux |
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2019-07-10 |
Eddie Hung | Error out if -abc9 and -retime specified |
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2019-07-10 |
Eddie Hung | Add some spacing |
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2019-07-10 |
Eddie Hung | Add some ASCII art explaining mux decomposition |
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2019-07-10 |
whitequark | attrmap: also consider process, switch and case attributes. |
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2019-07-10 |
Clifford Wolf | Merge pull request #1177 from YosysHQ/clifford/async |
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2019-07-10 |
Eddie Hung | Call muxpack and pmux2shiftx before cmp2lut |
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2019-07-09 |
Eddie Hung | Restore opt_clean back to original place |
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2019-07-09 |
Eddie Hung | Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6 |
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2019-07-09 |
David Shah | synth_ecp5: Fix typo in copyright header |
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2019-07-09 |
Clifford Wolf | Merge pull request #1174 from YosysHQ/eddie/fix1173 |
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2019-07-09 |
Clifford Wolf | Merge pull request #1175 from whitequark/write_verilog... |
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2019-07-09 |
Clifford Wolf | Fix tests/various/async FFL test |
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2019-07-09 |
Clifford Wolf | Improve tests/various/async, disable failing ffl test |
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2019-07-09 |
Eddie Hung | Extend using A[1] to preserve don't care |
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2019-07-09 |
Eddie Hung | Merge pull request #1171 from YosysHQ/revert-1166-eddie... |
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2019-07-09 |
Eddie Hung | Merge remote-tracking branch 'origin/eddie/fix1173... |
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2019-07-09 |
whitequark | write_verilog: fix placement of case attributes. NFC. |
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2019-07-09 |
Eddie Hung | Increment _TECHMAP_BITS_CONNMAP_ by one since counting... |
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2019-07-09 |
Clifford Wolf | Add tests/various/async.{sh,v} |
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2019-07-09 |
Clifford Wolf | Improve tests/various/run-test.sh |
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2019-07-09 |
Clifford Wolf | Add tests/simple_abc9/.gitignore |
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2019-07-09 |
whitequark | write_verilog: write RTLIL::Sa aka - as Verilog ?. |
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2019-07-09 |
Eddie Hung | Extend during mux decomposition with 1'bx |
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2019-07-09 |
Eddie Hung | Fix typo and comments |
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2019-07-09 |
Eddie Hung | Merge pull request #1170 from YosysHQ/eddie/fix_double_... |
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2019-07-09 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xc7mux |
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2019-07-09 |
Eddie Hung | synth_xilinx to call commands of synth -coarse directly |
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2019-07-09 |
Eddie Hung | Revert "synth_xilinx to call "synth -run coarse" with... |
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2019-07-09 |
Eddie Hung | Revert "Add "synth -keepdc" option" |
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2019-07-09 |
Eddie Hung | Rename __builtin_bswap32 -> bswap32 |
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2019-07-09 |
Eddie Hung | Fix spacing |
commit | commitdiff | tree |
2019-07-09 |
Eddie Hung | Fix spacing |
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2019-07-09 |
Clifford Wolf | Merge pull request #1168 from whitequark/bugpoint-processes |
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2019-07-09 |
Clifford Wolf | Merge pull request #1169 from whitequark/more-proc... |
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2019-07-09 |
Clifford Wolf | Merge pull request #1163 from whitequark/more-case... |
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2019-07-09 |
Clifford Wolf | Merge pull request #1162 from whitequark/rtlil-case... |
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2019-07-09 |
Clifford Wolf | Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup |
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2019-07-09 |
whitequark | proc_prune: promote assigns to module connections when... |
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2019-07-09 |
whitequark | proc_prune: new pass. |
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2019-07-09 |
whitequark | bugpoint: add -assigns and -updates options. |
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2019-07-09 |
whitequark | proc_clean: add -quiet option. |
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next |