2019-12-28 |
Eddie Hung | write_xaiger: inherit port ordering from original module |
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2019-12-28 |
Eddie Hung | Revert "Merge pull request #1598 from YosysHQ/revert... |
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2019-12-27 |
Eddie Hung | Merge branch 'master' of github.com:YosysHQ/yosys |
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2019-12-27 |
Eddie Hung | write_xaiger: simplify c{i,o}_bits |
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2019-12-27 |
David Shah | Merge pull request #1598 from YosysHQ/revert-1588-eddie... |
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2019-12-27 |
David Shah | Revert "write_xaiger: only instantiate each whitebox... |
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2019-12-25 |
Miodrag Milanovic | fixed invalid char |
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2019-12-25 |
Marcin Kościelnicki | iopadmap: Emit tristate buffers with const OE for some... |
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2019-12-25 |
Marcin Kościelnicki | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen |
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2019-12-25 |
Marcin Kościelnicki | Minor nit fixes |
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2019-12-23 |
Eddie Hung | Add DSP cascade tests |
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2019-12-23 |
Eddie Hung | Fix OPMODE for PCIN->PCOUT cascades in xc6s, check... |
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2019-12-23 |
Eddie Hung | Fix CEA/CEB check |
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2019-12-23 |
Eddie Hung | Fix checking CE[AB] and for direct connections |
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2019-12-23 |
Eddie Hung | Support unregistered cascades for A and B inputs |
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2019-12-23 |
Eddie Hung | Add DSP48A* PCOUT -> PCIN cascade support |
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2019-12-23 |
Marcin Kościelnicki | xilinx: Test our DSP48A/DSP48A1 simulation models. |
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2019-12-22 |
Marcin Kościelnicki | xilinx_dsp: Initial DSP48A/DSP48A1 support. |
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2019-12-20 |
Eddie Hung | Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup |
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2019-12-20 |
Eddie Hung | Add abc9_arrival times for RAM{32,64}M |
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2019-12-20 |
Eddie Hung | Add RAM{32,64}M to abc9_map.v |
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2019-12-20 |
Eddie Hung | Put specify/endspecify inside `` |
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2019-12-20 |
Eddie Hung | Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut |
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2019-12-20 |
Eddie Hung | write_xaiger: only instantiate each whitebox cell type... |
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2019-12-20 |
Eddie Hung | Merge pull request #1587 from YosysHQ/revert-1558-eddie... |
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2019-12-20 |
Eddie Hung | Revert "Optimise write_xaiger" |
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2019-12-20 |
Graham Edgecombe | Fix linking with Python 3.8 |
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2019-12-20 |
Graham Edgecombe | Add PYTHON_CONFIG variable to the Makefile |
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2019-12-19 |
Eddie Hung | Merge pull request #1581 from YosysHQ/clifford/fix1565 |
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2019-12-19 |
Eddie Hung | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup |
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2019-12-19 |
Eddie Hung | Merge pull request #1569 from YosysHQ/eddie/fix_1531 |
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2019-12-19 |
Eddie Hung | Merge pull request #1571 from YosysHQ/eddie/fix_1570 |
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2019-12-19 |
Marcin Kościelnicki | xilinx: Add simulation models for remaining CLB primitives. |
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2019-12-19 |
Marcin Kościelnicki | xilinx_dffopt: Keep order of LUT inputs. |
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2019-12-18 |
Eddie Hung | Interpret "abc9 -lut" as lut string only if [0-9:] |
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2019-12-18 |
Eddie Hung | Add "scratchpad" to CHANGELOG |
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2019-12-18 |
Eddie Hung | Merge branch 'master' of github.com:YosysHQ/yosys |
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2019-12-18 |
David Shah | Merge pull request #1563 from YosysHQ/dave/async-prld |
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2019-12-18 |
Eddie Hung | Merge pull request #1572 from nakengelhardt/scratchpad_pass |
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2019-12-18 |
Eddie Hung | Merge pull request #1584 from YosysHQ/mwk/xilinx-flaky... |
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2019-12-18 |
Marcin Kościelnicki | tests/xilinx: fix flaky mux test |
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2019-12-18 |
Marcin Kościelnicki | xilinx: Add xilinx_dffopt pass (#1557) |
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2019-12-18 |
Marcin Kościelnicki | xilinx: Improve flip-flop handling. |
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2019-12-18 |
Clifford Wolf | Send people to symbioticeda.com instead of verific.com |
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2019-12-18 |
N. Engelhardt | use extra_args |
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2019-12-17 |
Clifford Wolf | Fix sim for assignments with lhs<rhs size, fixes #1565 |
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2019-12-17 |
Eddie Hung | Cleanup |
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2019-12-17 |
Eddie Hung | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram |
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2019-12-17 |
Eddie Hung | Merge pull request #1521 from dh73/diego/memattr |
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2019-12-17 |
Eddie Hung | Enforce non-existence |
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2019-12-16 |
Eddie Hung | Update doc |
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2019-12-16 |
Eddie Hung | Add another test |
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2019-12-16 |
Eddie Hung | More sloppiness, thanks @dh73 for spotting |
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2019-12-16 |
Eddie Hung | Accidentally commented out tests |
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2019-12-16 |
Eddie Hung | Add unconditional match blocks for force RAM |
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2019-12-16 |
Eddie Hung | Oops |
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2019-12-16 |
Eddie Hung | Merge blockram tests |
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2019-12-16 |
Eddie Hung | Update xc7/xcu bram rules |
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2019-12-16 |
Eddie Hung | Implement 'attributes' grammar |
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2019-12-16 |
Eddie Hung | Merge branch 'diego/memattr' of https://github.com... |
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2019-12-16 |
Eddie Hung | Merge branch 'eddie/xilinx_lutram' of github.com:YosysH... |
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2019-12-16 |
Eddie Hung | Populate DID/DOD even if unused |
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2019-12-16 |
Eddie Hung | Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q |
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2019-12-16 |
Diego H | Fixing compiler warning/issues. Moving test script... |
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2019-12-16 |
N. Engelhardt | add assert option to scratchpad command |
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2019-12-16 |
Diego H | Removing fixed attribute value to !ramstyle rules |
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2019-12-16 |
Diego H | Merging attribute rules into a single match block;... |
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2019-12-16 |
Eddie Hung | Merge pull request #1575 from rodrigomelo9/master |
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2019-12-16 |
Eddie Hung | Merge pull request #1577 from gromero/for-yosys |
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2019-12-16 |
Eddie Hung | Merge pull request #1578 from noopwafel/eqneq-debug |
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2019-12-15 |
Alyssa Milburn | Fix opt_expr.eqneq.cmpzero debug print |
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2019-12-13 |
Diego H | Refactoring memory attribute matching based on IEEE... |
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2019-12-13 |
Eddie Hung | Merge pull request #1533 from dh73/bram_xilinx |
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2019-12-13 |
Eddie Hung | Disable RAM16X1D test |
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2019-12-13 |
Eddie Hung | Disable RAM16X1D match rule; carry-over from LUT4 arches |
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2019-12-13 |
Eddie Hung | RAM64M8 to also have [5:0] for address |
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2019-12-13 |
Diego H | Renaming BRAM memory tests for the sake of uniformity |
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2019-12-13 |
Rodrigo Alejandro... | Fixed some missing "verilog_" in documentation |
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2019-12-13 |
N. Engelhardt | add periods and newlines to help message |
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2019-12-13 |
Eddie Hung | Remove extraneous synth_xilinx call |
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2019-12-13 |
Eddie Hung | Add tests for these new models |
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2019-12-13 |
Eddie Hung | Add RAM32X6SDP and RAM64X3SDP modes |
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2019-12-13 |
Eddie Hung | Fix RAM64M model to have 6 bit address bus |
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2019-12-13 |
Eddie Hung | Add #1460 testcase |
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2019-12-13 |
Eddie Hung | Add memory rules for RAM16X1D, RAM32M, RAM64M |
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2019-12-13 |
Eddie Hung | Rename memory tests to lutram, add more xilinx tests |
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2019-12-12 |
Diego H | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB3... |
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2019-12-12 |
Eddie Hung | abc9_map.v: fix Xilinx LUTRAM |
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2019-12-12 |
Diego H | Adding a note (TODO) in the memory_params.ys check... |
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2019-12-12 |
N. Engelhardt | add test and make help message more verbose |
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2019-12-12 |
Diego H | Updating RAMB36E1 thresholds. Adding test for both... |
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2019-12-12 |
Diego H | Merge https://github.com/YosysHQ/yosys into bram_xilinx |
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2019-12-12 |
Eddie Hung | Make SV2017 compliant courtesy of @wsnyder |
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2019-12-12 |
N. Engelhardt | add a command to read/modify scratchpad contents |
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2019-12-12 |
Eddie Hung | Stray log_dump |
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2019-12-12 |
Eddie Hung | Preserve size of $genval$-s in for loops |
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2019-12-12 |
Eddie Hung | Add testcase |
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2019-12-12 |
Eddie Hung | Update README.md :: abc_ -> abc9_ |
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2019-12-11 |
Eddie Hung | Fix bitwidth mismatch; suppresses iverilog warning |
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2019-12-11 |
Gustavo Romero | manual: Fix text in Abstract section |
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