yosys.git
2020-05-28 whitequarkMerge pull request #2051 from Xiretza/makefile-cd-warning
2020-05-28 whitequarkMerge pull request #2031 from epfl-vlsc/master
2020-05-28 whitequarkMerge pull request #2063 from boqwxp/techmapped-firrtl
2020-05-28 whitequarkMerge pull request #2088 from rswarbrick/count-at
2020-05-28 whitequarkMerge pull request #2087 from rswarbrick/lex-warn
2020-05-28 whitequarkMerge pull request #2086 from rswarbrick/sigbit
2020-05-28 whitequarkMerge pull request #2084 from rswarbrick/c_str
2020-05-26 whitequarkMerge pull request #2090 from whitequark/cxxrtl-fixes
2020-05-26 whitequarkcxxrtl: make logging a little bit nicer.
2020-05-26 whitequarkcxxrtl: add missing parts of commit 281c9685.
2020-05-26 Rupert SwarbrickSilence spurious warning in Verilog lexer when compilin...
2020-05-26 Rupert SwarbrickMinor optimisation in Module::wire() and Module::cell()
2020-05-26 Rupert SwarbrickUse default copy constructor for RTLIL::SigBit
2020-05-26 Rupert SwarbrickUse c_str(), not str() for IdString/std::string ==...
2020-05-25 Eddie HungMerge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
2020-05-25 Eddie Hungtests: xilinx macc test to have initval, shorten BMC...
2020-05-25 Eddie Hungxilinx: tidy up cells_sim.v a little
2020-05-25 Eddie HungMerge pull request #2044 from YosysHQ/eddie/fix2037
2020-05-25 Eddie Hungverilog: move attr from simple_behav_stmt to its childr...
2020-05-25 Eddie Hungtest: add attribute-before-stmt test from @nakengelhardt
2020-05-25 Eddie Hungverilog: do not warn for attributes on null statements
2020-05-25 Eddie Hungtests: add an generate-else test too
2020-05-25 Eddie Hungverilog: handle empty generate statement by removing...
2020-05-25 Eddie Hungverilog: fix #2037 by permitting (and freeing) attribut...
2020-05-25 Eddie Hungtests: add #2037 testcase
2020-05-25 clairexenMerge pull request #2015 from boqwxp/qbfsat-bisection
2020-05-24 Eddie HungMerge pull request #2075 from YosysHQ/eddie/xaiger_cleanup
2020-05-24 Eddie Hungxaiger: add testcase
2020-05-24 Eddie Hungxaiger: do not derive cells
2020-05-23 Eddie HungMerge pull request #2074 from YosysHQ/eddie/ecp5_cleanup
2020-05-23 Eddie Hungecp5: cleanup unused +/ecp5/abc9_model.v
2020-05-23 Alberto Gonzalezqbfsat: Remove cruft inadvertently left untouched in...
2020-05-23 Alberto Gonzalezqbfsat: Add bisection mode and make it the default.
2020-05-22 whitequarkMerge pull request #2072 from whitequark/cxxrtl-dont...
2020-05-22 whitequarkcxxrtl: get rid of -O5 aka `opt_clean -purge` optimizat...
2020-05-22 Eddie Hungabc9_ops: update comment
2020-05-21 Eddie HungMerge pull request #2057 from YosysHQ/eddie/fix_task_attr
2020-05-21 Eddie HungUpdate frontends/verilog/verilog_parser.y
2020-05-21 Miodrag MilanovićMerge pull request #2059 from boqwxp/logger-vector...
2020-05-20 N. EngelhardtMerge pull request #2046 from PeterCrozier/trap
2020-05-20 N. EngelhardtMerge pull request #2054 from boqwxp/fix-smtbmc
2020-05-19 Alberto Gonzalezsmtbmc: Fix typo in error message.
2020-05-18 Marcelina KościelnickaAdd force_downto and force_upto wire attributes.
2020-05-18 Eddie HungMerge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
2020-05-17 Alberto Gonzalezfirrtl: Accept techmapped cell types in FIRRTL backend.
2020-05-17 Claire WolfRevert "Add support for non-power-of-two mem chunks...
2020-05-15 Alberto Gonzalezlog: Use `dict` instead of `std::vector<std::pair>...
2020-05-14 Eddie Hungabc9: use (* abc9_keep *) instead of (* abc9_scc *...
2020-05-14 Eddie Hungverilog: attributes before task enable (but 13 s/r...
2020-05-14 Eddie Hungtests: attributes before task enable
2020-05-14 Eddie HungMerge pull request #2055 from YosysHQ/eddie/logger_multiple
2020-05-14 Eddie Hungopt_expr: Sx to Sz; spotted by @Xiretza
2020-05-14 Eddie HungMerge pull request #1994 from YosysHQ/eddie/fix_bug1758
2020-05-14 Eddie Hunglogger: clean up doc
2020-05-14 Eddie Hungabc9_ops: -prep_hier to create unmap module that remove...
2020-05-14 Eddie Hungabc9: preserve $_DFF_?_.Q's (* init *); rely on clean...
2020-05-14 Eddie HungFix broken test when ignoring abc9_flop with init ...
2020-05-14 Eddie Hungabc9_ops/xaiger: further reducing Module::derive()...
2020-05-14 Eddie HungCleanup; reduce Module::derive() calls
2020-05-14 Eddie Hungecp5: latches_map.v if *not* -asyncprld
2020-05-14 Eddie Hungecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un...
2020-05-14 Eddie Hungecp5: fix rebase mistake
2020-05-14 Eddie Hungabc9: update to =_$abc9_flops pattern which includes...
2020-05-14 Eddie Hungabc9_ops: update docs
2020-05-14 Eddie Hungxilinx: gate specify/attributes from iverilog
2020-05-14 Eddie Hungabc9: only do +/abc9_map if `DFF
2020-05-14 Eddie Hungabc9: rework submod -- since it won't move (* keep...
2020-05-14 Eddie Hungecp5: TRELLIS_FF bypass path only in async mode
2020-05-14 Eddie Hungtiminginfo: ignore $specify2 cells if EN is false
2020-05-14 Eddie Hungxilinx/ice40/ecp5: zinit requires selected wires, so...
2020-05-14 Eddie Hungabc9_ops: move assert
2020-05-14 Eddie Hungabc9: put 'aigmap' back
2020-05-14 Eddie Hungxilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able...
2020-05-14 Eddie Hungabc9_ops: fix bypass boxes using (* abc9_bypass *)
2020-05-14 Eddie Hungabc9_ops: tidy up, suppress error if no boxes/holes
2020-05-14 Eddie Hungabc9_ops: -prep_delays to not insert delay box if input...
2020-05-14 Eddie Hungabc9_ops: cleanup; -prep_dff -> -prep_dff_submod
2020-05-14 Eddie Hungabc9_ops: add -prep_bypass for auto bypass boxes; refactor
2020-05-14 Eddie Hungabc9_ops: -reintegrate to handle $_FF_; cleanup
2020-05-14 Eddie Hungxaiger: no longer use nonstandard even/odd to designate...
2020-05-14 Eddie Hungaiger: -xaiger to return $_FF_ flops
2020-05-14 Eddie Hungabc9: not enough to techmap_fail on (* init=1 *), hide...
2020-05-14 Eddie Hungabc9: test to use box file instead of auto
2020-05-14 Eddie Hungabc9: restore selected_modules()
2020-05-14 Eddie Hungsynth_*: no need to explicitly read +/abc9_model.v
2020-05-14 Eddie HungRevert "Merge pull request #1917 from YosysHQ/eddie...
2020-05-14 Eddie Hungabc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 Eddie Hungkernel: TimingInfo to clamp -ve setup/edge-sensitive...
2020-05-14 Eddie Hungabc9_ops: -prep_dff_map to error if async flop found
2020-05-14 Eddie HungUncomment negative setup times; clamp to zero for conne...
2020-05-14 Eddie Hungabc9: remove redundant wbflip
2020-05-14 Eddie Hungxaiger: always sort input/output bits by port id
2020-05-14 Eddie Hungabc9: generate $abc9_holes design instead of <name...
2020-05-14 Eddie Hungabc9_ops: more robust
2020-05-14 Eddie Hungabc9: suppress warnings when no compatible + used flop...
2020-05-14 Eddie Hungxilinx: update abc9_dff tests
2020-05-14 Eddie Hungxilinx: remove no-longer-relevant test
2020-05-14 Eddie Hungaiger/xaiger: use odd for negedge clk, even for posedge
2020-05-14 Eddie Hungabc9: cleanup
2020-05-14 Eddie HungRevert "ecp5: replace ecp5_ffinit with techmap rules...
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