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gem5.git
2012-05-19
Gabe Black
Syscalls: warn when the length argument to mmap is...
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2012-05-15
Lena Olson
Mem: Fix size check when allocating physical memory
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2012-05-16
Andreas Hansson
Config: Fix a typo in the se.py script for setting...
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2012-05-10
Ali Saidi
ARM: update stats for clock frequency fix.
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2012-05-10
Koan-Sin Tan
ARM: fix the calculation of the values in the RV clocks
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2012-05-10
Ali Saidi
stats: fix compilation of unit test.
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2012-05-10
Ali Saidi
stats: fix bug in assert for 2d vector
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2012-05-10
Chander Sudanthi
ARM: pl011 raw interrupt fix
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2012-05-10
Chander Sudanthi
ARM: EMM board address range fix
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2012-05-10
Uri Wiener
DOT: improved dot-based system visualization
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2012-05-10
Uri Wiener
DOT: fixed broken code for visualizing configuration...
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2012-05-10
Dam Sunwoo
ARM: guard masked symbol tables by default
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2012-05-10
Ali Saidi
mem: fix bug with CopyStringOut and null string termina...
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2012-05-10
Ali Saidi
Cache: restructure code that actually isn't a loop
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2012-05-10
Ali Saidi
dev: use correct delete operation in SimpleDisk
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2012-05-10
Ali Saidi
ARM: Fix incorrect use of not operators in arm devices
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2012-05-10
Ali Saidi
gem5: assert before indexing intro arrays to verify...
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2012-05-10
Ali Saidi
gem5: fix some iterator use and erase bugs
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2012-05-10
Ali Saidi
gem5: fix a number of use after free issues
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2012-05-10
Ali Saidi
base: fix a invalid ?: operator
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2012-05-10
Ali Saidi
gem5: Fix a number of incorrect case statements
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2012-05-10
Ali Saidi
ARM: Update m5op assembly for thumb compilation.
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2012-05-10
Ali Saidi
stats: track if the stats have been enabled and prevent...
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2012-05-10
Ali Saidi
Cache: Panic if you attempt to create a checkpoint...
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2012-05-10
Pritha Ghoshal
IGbE: Fix writeback conditions for i8254x GbE in update...
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2012-05-09
Nathan Binkert
stats: update stats for no_value -> nan
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2012-05-09
Nathan Binkert
stats: use nan instead of no_value
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2012-05-09
Andreas Hansson
MEM: Add the communication monitor
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2012-05-08
Steve Reinhardt
scons: allow override of SWIG binary on command line
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2012-05-08
Andreas Hansson
MEM: Do not forward uncacheable to bus snoopers
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2012-05-04
Andreas Hansson
Ruby: Ensure snoop requests are sent using sendTimingSn...
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2012-05-04
Nilay Vaish
Regression: Move x86 fs ruby simulation from quick...
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2012-05-03
Jayneel Gandhi
Config: Fix help msg for option --mem-size
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2012-05-01
Andreas Hansson
MEM: Separate requests and responses for timing accesses
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2012-04-30
Nilay Vaish
Regression: Stats update for X86 Ruby FS test
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2012-04-29
Gabe Black
X86: Fix the IMUL_R_P_I macroop.
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2012-04-29
Vince Weaver
X86: Fix up the open system call's flags.
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2012-04-29
Vince Weaver
X86: Make gem5 ignore a bunch of syscalls.
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2012-04-28
Nilay Vaish
Garnet: Correct computation of link utilization
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2012-04-27
Nilay Vaish
util/regress: Add the missing comma in the list of...
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2012-04-26
Nilay Vaish
Regression: Add a test for x86 timing full system ruby...
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2012-04-25
Nilay Vaish
Ruby: Remove extra statements from Sequencer
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2012-04-25
Andreas Hansson
MEM: Use base class Master/SlavePort pointers in the bus
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2012-04-25
Andreas Hansson
MEM: Add the PortId type and a corresponding id field...
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2012-04-25
Andreas Hansson
clang/gcc: Use STL hash function for int64_t and uint64_t
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2012-04-24
Gabe Black
X86: Update stats for the slightly changed TLB behavior.
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2012-04-24
Gabe Black
X86: Clear out duplicate TLB entries when adding a...
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2012-04-23
Gabe Black
ISA: Put parser generated files in a "generated" directory.
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2012-04-23
Steve Reinhardt
scons: update minimum SWIG version to 1.3.34
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2012-04-22
Gabe Black
base: Include cassert in trie.hh.
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2012-04-21
Gabe Black
X86: Report an error if there's no kernel object, don...
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2012-04-17
Jayneel Gandhi
SE Config: Changed se.py to support multithreaded mode
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2012-04-16
Jayneel Gandhi
Config: Add command line options for disk image and...
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2012-04-15
Gabe Black
CPU: Tidy up some formatting and a DPRINTF in the simpl...
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2012-04-15
Gabe Black
X86: Fix a tiny typo in the load/store microop constructor.
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2012-04-15
Gabe Black
X86: Use the AddrTrie class to implement the TLB.
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2012-04-15
Gabe Black
sim: Update some comments in trie.hh that were meant...
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2012-04-15
Gabe Black
sim: A trie data structure specifically to speed up...
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2012-04-14
Andreas Hansson
Ruby: Use MasterPort base-class pointers where possible
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2012-04-14
Andreas Hansson
MEM: Remove the Broadcast destination from the packet
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2012-04-14
Andreas Hansson
MEM: Separate snoops and normal memory requests/responses
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2012-04-14
Andreas Hansson
Regression: Add ANSI colours to highlight test status
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2012-04-14
Andreas Hansson
clang/gcc: Fix compilation issues with clang 3.0 and...
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2012-04-13
Steve Reinhardt
SCons: restore Werror option in src/SConscript
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2012-04-12
Andreas Hansson
Stats: Update with use of std::map for ordered iteratio...
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2012-04-12
Andreas Hansson
Ruby: Ensure order-dependent iteration uses an ordered map
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2012-04-10
Gabe Black
tests: Fix building unit tests.
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2012-04-07
Brad Beckmann
rubytest: remove spurious printf
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2012-04-06
Brad Beckmann
regress: ruby random tester and hammer stats updates
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2012-04-06
Brad Beckmann
ruby: set SimpleTiming as the default cpu
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2012-04-06
Lisa Hsu
slicc: Controllers attached to Sequencers no longer...
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2012-04-06
Brad Beckmann
sim-ruby: checkpointing fixes and dependent eventq...
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2012-04-06
Brad Beckmann
slicc: fixed error message when the type has no inheritance
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2012-04-06
Brad Beckmann
MOESI_hammer: tbe allocation and dependent wakeup fixes
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2012-04-06
Brad Beckmann
python: added __nonzero__ function to SimObject Bool...
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2012-04-06
Brad Beckmann
MOESI_hammer: fixed bug with single cpu + flushes,...
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2012-04-06
Brad Beckmann
rubytest: seperated read and write ports.
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2012-04-06
Andreas Hansson
MEM: Enable multiple distributed generalized memories
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2012-04-05
Tushar Krishna
NetworkTest: remove unnecessary memory allocation
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2012-04-05
Nilay Vaish
Config: corrects the way Ruby attaches to the DMA ports
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2012-04-05
Andreas Hansson
Ruby: Fix the example configurations option parsing
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2012-04-05
Andreas Hansson
Python: Make the All proxy traverse SimObject children...
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2012-04-03
Andreas Hansson
Atomic: Remove the physmem_port and access memory directly
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2012-03-31
Gabe Black
X86: Fix address size handling so real mode works properly.
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2012-03-30
Andreas Hansson
MEM: Remove legacy DRAM in preparation for memory updates
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2012-03-30
Andreas Hansson
Ruby: Remove the physMemPort and instead access memory...
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2012-03-30
William Wang
MEM: Introduce the master/slave port sub-classes in C++
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2012-03-30
Andreas Hansson
CPU: Unify initMemProxies across CPUs and simulation...
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2012-03-28
Nilay Vaish
Config: Change the way options are added
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2012-03-27
Nilay Vaish
Config: Move setWorkCountOptions() to Simulation.py
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2012-03-26
Andreas Hansson
range_map: Enable const find and iteration
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2012-03-26
Andreas Hansson
Power: Change bitfield name to avoid conflicts with...
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2012-03-23
Andreas Hansson
Ruby: Fix Set::print for 32-bit hosts
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2012-03-22
Andreas Hansson
MEM: Unify bus access methods and prepare for master...
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2012-03-22
Andreas Hansson
MEM: Split SimpleTimingPort into PacketQueue and ports
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2012-03-22
Andreas Hansson
Scons: Remove Werror=False in SConscript files
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2012-03-21
Andreas Hansson
Python: Fix a conditional expression that requires...
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2012-03-21
Ali Saidi
ARM: Update stats for IT and conditional branch changes
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2012-03-21
Nathanael Premillieu
ARM: Fix case where cond/uncond control is mis-specified
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2012-03-21
Ali Saidi
ARM: Clean up condCodes in IT blocks.
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