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yosys.git
2018-03-07
Clifford Wolf
Set Verific db_preserve_user_nets flag
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2018-03-07
Clifford Wolf
Add Xilinx RAM64X1D and RAM128X1D simulation models
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2018-03-06
Clifford Wolf
Add "memory_nordff" pass
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2018-03-06
Clifford Wolf
Update comment about supported SVA in verificsva.cc
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2018-03-06
Clifford Wolf
Add SVA NON_CONSECUTIVE_REPEAT and GOTO_REPEAT support
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2018-03-06
Clifford Wolf
Add SVA first_match() support
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2018-03-06
Clifford Wolf
Add SVA within support
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2018-03-06
Clifford Wolf
Add support for SVA sequence intersect
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2018-03-06
Clifford Wolf
Add get_fsm_accept_reject for parsing SVA properties
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2018-03-06
Clifford Wolf
Simplified SVA "until" handling
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2018-03-05
Clifford Wolf
Imporove yosys-smtbmc error handling, Improve VCD output
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2018-03-04
Clifford Wolf
Fix connwrappers help message
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2018-03-04
Clifford Wolf
Improve handling of warning messages
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2018-03-04
Clifford Wolf
Update copyright header
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2018-03-04
Clifford Wolf
Improve SMT2 encoding of $reduce_{and,or,bool}
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2018-03-04
Clifford Wolf
Fix a hangup in yosys-smtbmc error handling
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2018-03-04
Clifford Wolf
Add proper SVA seq.triggered support
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2018-03-04
Clifford Wolf
Add "synth -noshare"
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2018-03-04
Clifford Wolf
Add Verific SVA support for "seq and seq" expressions
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2018-03-04
Clifford Wolf
Refactor Verific SVA importer property parser
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2018-03-04
Clifford Wolf
Add VerificClocking class and refactor Verific DFF...
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2018-03-03
Clifford Wolf
Improved error handling in yosys-smtbmc
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2018-03-03
Clifford Wolf
Add SVA support for sequence OR
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2018-03-03
Clifford Wolf
Terminate running SMT solver when smtbmc is terminated
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2018-03-03
Clifford Wolf
Fix smtbmc smtc/aiw parser for wire names containing []
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2018-03-02
Clifford Wolf
Fix handling of SVA "until seq.triggered" properties
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2018-03-02
Clifford Wolf
Update SVA cheat sheet in verificsva.cc
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2018-03-01
Clifford Wolf
Fix in Verific SVA importer handling of until_with
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2018-03-01
Clifford Wolf
Mangle names with square brackets in VCD files to work...
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2018-03-01
Clifford Wolf
Fixes and improvements in Verific SVA importer
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2018-03-01
Clifford Wolf
Add $rose/$fell support to Verific bindings
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2018-02-28
Clifford Wolf
Merge branch 'verificsva-ng'
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2018-02-28
Clifford Wolf
Add support for PRIM_SVA_UNTIL to new SVA importer
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2018-02-28
Clifford Wolf
Add DFSM generator to verific SVA importer
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2018-02-28
Clifford Wolf
Continue refactoring of Verific SVA importer code
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2018-02-27
Clifford Wolf
Major redesign of Verific SVA importer
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2018-02-27
Clifford Wolf
Add -lz for verific builds
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2018-02-26
Clifford Wolf
Add handling of verific OPER_REDUCE_NOR
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2018-02-26
Clifford Wolf
Add handling of verific OPER_SELECTOR and OPER_WIDE_SEL...
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2018-02-26
Clifford Wolf
Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX
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2018-02-26
Clifford Wolf
Add "SVA syntax cheat sheet" comment to verificsva.cc
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2018-02-26
Clifford Wolf
Add $dlatchsr support to clk2fflogic
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2018-02-26
Clifford Wolf
Small fixes and improvements in $allconst/$allseq handling
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2018-02-26
Clifford Wolf
Fix opt_rmdff handling of $dlatchsr
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2018-02-23
Clifford Wolf
Merge branch 'forall'
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2018-02-23
Clifford Wolf
Add smtbmc support for exist-forall problems
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2018-02-23
Clifford Wolf
Add $allconst and $allseq cell types
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2018-02-22
Clifford Wolf
Add Verific SVA support for ranges in repetition operator
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2018-02-21
Clifford Wolf
Add support for SVA throughout via Verific
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2018-02-20
Clifford Wolf
Add support for mockup clock signals in yosys-smtbmc...
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2018-02-19
Clifford Wolf
Merge pull request #507 from cr1901/msys2
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2018-02-19
William D....
Improve msys2 flags for building abc.
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2018-02-18
Clifford Wolf
Add support for SVA sequence concatenation ranges via...
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2018-02-18
Clifford Wolf
Add support for SVA until statements via Verific
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2018-02-18
Clifford Wolf
Move Verific SVA importer to extra C++ source file
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2018-02-18
Clifford Wolf
Merge Verific SVA preprocessor and SVA importer
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2018-02-16
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2018-02-15
Clifford Wolf
Improve handling of "bus" pins in liberty front-end...
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2018-02-15
Clifford Wolf
Fix verific PRIM_SVA_AT handling in properties with...
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2018-02-13
Clifford Wolf
Fixed yosys-config for binary distributions with Verific
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2018-02-13
Clifford Wolf
Recognize stand-alone obj pattern even when it contains...
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2018-02-08
Clifford Wolf
Fix handling of zero-length cell connections in SMT2...
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2018-02-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2018-02-03
Clifford Wolf
Do not create deep backtraces unless in ENABLE_DEBUG...
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2018-02-03
Clifford Wolf
Merge pull request #488 from azonenberg/for_clifford
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2018-02-03
Clifford Wolf
Fixed gcc 7.2 "statement will never be executed" warning
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2018-02-01
Clifford Wolf
Fix single-bit $stable handling in verific front-end
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2018-01-31
Clifford Wolf
Add Verific attribute handling for assert/assume/cover...
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2018-01-29
Clifford Wolf
Fix smtio.py for large SMT2 S-expressions
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2018-01-28
Clifford Wolf
Fix permissions on verific vdb files
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2018-01-23
Clifford Wolf
Fixed handling of synchronous and asynchronous assertio...
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2018-01-19
Clifford Wolf
Use "strip -S" instead of "strip -d" for Mac OS X compa...
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2018-01-19
Clifford Wolf
Improve log messages in equiv_make
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2018-01-18
Clifford Wolf
Move user-provided smt2 info stmts to the top of the...
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2018-01-18
Robert Ou
coolrunner2: Move LOC attributes onto the IO cells
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2018-01-17
Clifford Wolf
Strip debug symbols from binaries on install
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2018-01-09
Clifford Wolf
Add "dffinit -highlow" and fix synth_intel
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2018-01-07
Clifford Wolf
Add support for "yosys -E"
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2018-01-07
Clifford Wolf
Bugfix in hierarchy blackbox module port width handling
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2018-01-07
Clifford Wolf
Update ABC to hg rev 6e3c24b3308a
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2018-01-05
Clifford Wolf
Merge pull request #479 from Fatsie/latch_without_data
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2018-01-05
Clifford Wolf
Bugfix in hierarchy handling of blackbox module ports
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2018-01-04
Clifford Wolf
Merge pull request #480 from Fatsie/liberty_value_expre...
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2018-01-04
Clifford Wolf
Temporarily derive blackbox modules in hierarchy to...
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2018-01-03
Staf Verhaegen
Value of properties can be expression.
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2018-01-03
Staf Verhaegen
Some standard cell libraries include a latch with only...
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2017-12-24
Clifford Wolf
Add "no driver for signal bit" error msg to btor back-end
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2017-12-24
Clifford Wolf
Bugfix in verilog_defaults argument parser
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2017-12-19
Clifford Wolf
Fix minor typo in "prep" help message
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2017-12-17
Clifford Wolf
Simple fix BTOR memory encoding
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2017-12-17
Clifford Wolf
Improve BTOR memory encoding
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2017-12-15
Clifford Wolf
Merge branch 'btor-ng'
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2017-12-15
Clifford Wolf
Add array support to btor back-end
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2017-12-14
Clifford Wolf
Add $anyconst/$anyseq support to btor back-end
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2017-12-14
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-14
Clifford Wolf
Add yosys-smtbmc VCD writer support for memories with...
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2017-12-14
Clifford Wolf
Fix a bug in clk2fflogic memory handling
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2017-12-14
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-14
Clifford Wolf
Add clk2fflogic memory support
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2017-12-14
Clifford Wolf
Add smt2 back-end support for async write memories
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