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yosys.git
2014-12-21
Clifford Wolf
Fixed "abc" pass for clk and enable signals driven...
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2014-12-19
Clifford Wolf
Added DFFE support to "abc" pass
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2014-12-19
Clifford Wolf
Added $dffe support to write_verilog
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2014-12-19
Clifford Wolf
Checking existence of ports in "hierarchy -check"
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2014-12-19
Clifford Wolf
Fixed another bug in write_blif handling of $lut cells
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2014-12-17
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-12-17
Clifford Wolf
Fixed writing of $lut cells in BLIF backend
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2014-12-16
Clifford Wolf
Fixed build with gcc 4.6
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2014-12-14
Clifford Wolf
Added "write_blif -undef" and support for special ...
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2014-12-14
Clifford Wolf
Added "write_blif -blackbox"
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2014-12-14
Clifford Wolf
Added "blif -unbuf" feature
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2014-12-14
Clifford Wolf
Removed psmisc from deps list (usually fuser is already...
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2014-12-12
Clifford Wolf
Added psmisc to prerequisites
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2014-12-12
Clifford Wolf
Removed UTF-8 chars from techmap.v
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2014-12-12
Clifford Wolf
Added missing prerequisites to README
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2014-12-11
Clifford Wolf
Added IdString::destruct_guard hack
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2014-12-11
Clifford Wolf
Compile fix for visual studio
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2014-12-11
Clifford Wolf
Fixed supply0/supply1 with many wires
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2014-12-08
Clifford Wolf
Added functionality to dff2dffe pass
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2014-12-08
Clifford Wolf
Added bool constructors to SigBit and SigSpec
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2014-12-08
Clifford Wolf
Added module->addDffe() and module->addDffeGate()
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2014-12-08
Clifford Wolf
Added skeleton dff2dffe pass
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2014-12-08
Clifford Wolf
Added more documentation fixmes for nontrivial register...
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2014-12-08
Clifford Wolf
Added $dffe cell type
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2014-12-08
Clifford Wolf
Added $_DFFE_??_ cell types
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2014-12-07
Clifford Wolf
Merge branch 'master' of https://github.com/Martoni...
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2014-12-07
Fabien Marteau
manual/presentation.tex: bg option is unknown with...
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2014-12-06
Clifford Wolf
Merge pull request #43 from Martoni/master
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2014-12-05
Fabien Marteau
suppressing semi-colon at the end of dot files
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2014-12-04
Clifford Wolf
Added some missing .gitignore in manual/
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2014-11-27
Clifford Wolf
Fixed bug in "hierarchy -top" with array of instances
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2014-11-24
Clifford Wolf
Fixed minor bug in parsing delays
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2014-11-24
Clifford Wolf
Fixed two minor bugs in constant parsing
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2014-11-24
Clifford Wolf
Some fixes in stubnets example
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2014-11-20
Clifford Wolf
Merge pull request #42 from slowriot/master
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2014-11-20
SlowRiot
switching from unreliable typedefs to precisely sized...
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2014-11-20
SlowRiot
fixing incorrect buffer size allocation, and unsafe...
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2014-11-14
Clifford Wolf
Added warning for use of 'z' constants in HDL
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2014-11-12
Clifford Wolf
Fixed parsing of nested verilog concatenation and replicate
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2014-11-12
Clifford Wolf
Another 'make vcxsrc'
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2014-11-11
Clifford Wolf
Some fixed in "make vcxsrc" srcfiles.txt creation
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2014-11-11
Clifford Wolf
Split MXE "make dist" into MXE "make mxebin" and non...
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2014-11-09
Clifford Wolf
Added "yosys -qq" to also quiet warning messages
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2014-11-09
Clifford Wolf
Introducing YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NOR...
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2014-11-09
Clifford Wolf
Added log_warning() API
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2014-11-08
Clifford Wolf
Added automatic "make clean" to abc "hg pull" make...
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2014-11-08
Clifford Wolf
Some fixes in presentation
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2014-11-08
Clifford Wolf
Added missing fixup_ports() calls to "rename" command
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2014-11-08
Clifford Wolf
Use a cache for log_id() memory management
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2014-11-08
Clifford Wolf
Now we are in Yoys 0.4+ development
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2014-11-08
Clifford Wolf
Yosys 0.4
yosys-0.4
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2014-11-08
Clifford Wolf
Added "ENABLE_PLUGINS := 0" to verific amd64 build...
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2014-11-08
Clifford Wolf
Various documentation updates
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2014-11-08
Clifford Wolf
Added "Nx" syntax to "show" command for repeating SigChunks
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2014-11-07
Clifford Wolf
Added "used" attribute to entries in yosys_cover_list
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2014-11-07
Clifford Wolf
Minor corrections in CodingReadme
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2014-11-07
Clifford Wolf
Improved TopoSort determinism
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2014-11-07
Clifford Wolf
Fixed generation of temp names in verilog backend
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2014-11-07
Clifford Wolf
Updated ABC to 5b5af75f1dda
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2014-11-07
Clifford Wolf
Changelog for Yosys 0.4
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2014-11-07
Clifford Wolf
Fixed typo in "log_cmd_error_exception"
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2014-11-06
Clifford Wolf
Made "cover" a compile-time option (disabled by default)
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2014-11-05
Clifford Wolf
Removed QMAKE variable from Makefile
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2014-10-31
Clifford Wolf
Added "abc" label in synth script
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2014-10-31
Clifford Wolf
Added "opt -full" alias for all more aggressive optimiz...
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2014-10-30
Clifford Wolf
Fixed parsing of "module mymod #( parameter foo = 1...
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2014-10-30
Clifford Wolf
Improved nomem2reg documentation
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2014-10-29
Clifford Wolf
Added support for empty lines to here documents
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2014-10-29
Clifford Wolf
AST simplifier: optimize constant AST_CASE nodes before...
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2014-10-27
Clifford Wolf
Added support for task and function args in parentheses
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2014-10-26
Clifford Wolf
Improvements in $readmem[bh] implementation
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2014-10-26
Clifford Wolf
Added support for $readmemh/$readmemb
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2014-10-25
Clifford Wolf
Fixed constant "cond ? string1 : string2" with strings...
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2014-10-23
Clifford Wolf
Re-introduced Yosys::readsome() helper function
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2014-10-19
Clifford Wolf
minor indenting corrections
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2014-10-19
Clifford Wolf
Merge pull request #40 from parvizp/compile_mac_10.9.2
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2014-10-19
Parviz Palangpour
Builds on Mac 10.9.2 with LLVM 3.5.
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2014-10-18
Clifford Wolf
Improved new_id() for win32
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2014-10-18
Clifford Wolf
Also look for yosys-abc in parent dir on win32
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2014-10-18
Clifford Wolf
Various improvements to version reporting on win32
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2014-10-18
Clifford Wolf
Disabled READLINE in MXE cross build
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2014-10-18
Clifford Wolf
Fixed typo in test_cell
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2014-10-18
Clifford Wolf
Fixed shell prompt and proc_self_dirname() for win32
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2014-10-18
Clifford Wolf
Fixed various VS warnings
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2014-10-18
Clifford Wolf
Create vcxsrc in mxe build "make dist"
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2014-10-18
Clifford Wolf
Moved yosys-config.in to misc/
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2014-10-17
Clifford Wolf
Added notes regarding building in VS
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2014-10-17
Clifford Wolf
Added vcxproj_files.txt to MXE "make dist"
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2014-10-17
Clifford Wolf
More win32 (mxe and vs) build fixes
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2014-10-17
Clifford Wolf
Various win32 / vs build fixes
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2014-10-17
Clifford Wolf
Added genfiles.zip to MXE "make dist"
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2014-10-17
Clifford Wolf
Various MXE build fixes
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2014-10-17
William Speirs
Header changes so it will compile on VS
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2014-10-17
William Speirs
Wrapped math in int constructor
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2014-10-17
Clifford Wolf
Fixed a few VS warnings
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2014-10-16
Clifford Wolf
Don't be too smart with $dff cells with "init" attribut...
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2014-10-16
Clifford Wolf
Some cleanups in opt_clean
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2014-10-16
Clifford Wolf
Print "SystemVerilog" in "read_verilog -sv" log messages
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2014-10-15
Clifford Wolf
Fixed RTLIL::SigSpec::parse() for out-of-range bit...
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2014-10-15
Clifford Wolf
Fixed handling of invalid array access in mem2reg code
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