yosys.git
2019-08-15 Eddie HungMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
2019-08-15 Eddie HungffH -> ffFJKG
2019-08-14 Eddie HungFixes for reverting SigSpec helper functions
2019-08-14 Eddie HungPerform C -> PCIN optimisation after pattern matcher
2019-08-14 Eddie HungRevert changes to RTLIL::SigSpec methods
2019-08-13 Eddie HungOnly swap ports if $mul and not $__mul
2019-08-13 Eddie HungAdd assign PCOUT = P to DSP48E1
2019-08-13 Eddie HungRename to XilinxDspPass
2019-08-13 Eddie HungAdd DSP_A_MAXWIDTH_PARTIAL, refactor
2019-08-13 David Shahxilinx: Rework labels for faster Verilator testing
2019-08-12 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-12 Serge BazanskiMerge pull request #1152 from 1138-4EB/feat-docker
2019-08-12 Eddie HungMerge pull request #1277 from YosysHQ/eddie/fix_1262
2019-08-12 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-10 Eddie HungMerge pull request #1280 from YosysHQ/revert-1266-eddie...
2019-08-10 Eddie HungWrong way around
2019-08-10 David ShahRevert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 Eddie Hungcover_list -> cover as per @cliffordwolf
2019-08-10 Clifford WolfMerge pull request #1258 from YosysHQ/eddie/cleanup
2019-08-10 Clifford WolfMerge pull request #1261 from YosysHQ/clifford/verific_init
2019-08-10 Clifford WolfMerge pull request #1263 from ucb-bar/firrtl_err_on_uns...
2019-08-10 Clifford WolfMerge pull request #1270 from YosysHQ/eddie/alu_lcu_doc
2019-08-10 Clifford WolfMerge pull request #1272 from mmicko/travis_fix
2019-08-10 Clifford WolfMerge pull request #1274 from YosysHQ/eddie/fix_1271
2019-08-10 Clifford WolfMerge pull request #1276 from YosysHQ/clifford/fix1273
2019-08-10 Eddie HungCheck nusers of DSP output, not whole flop
2019-08-10 Eddie HungImprove ice40_dsp for non-fully-32-bit adders
2019-08-10 Eddie HungAdd wreduce to synth_ice40 -dsp as well
2019-08-09 Eddie HungAnother filter -> if
2019-08-09 Eddie HungCleanup
2019-08-09 Eddie HungPack partial-product adder DSP48E1 packing
2019-08-09 Eddie HungFix check
2019-08-09 Eddie HungRevert "Fix typo"
2019-08-09 Eddie HungGrammar
2019-08-09 Eddie HungReformat so it shows up/looks nice when "help $alu...
2019-08-09 Eddie HungSeparate $alu handling
2019-08-09 Eddie HungAdd $alu tests
2019-08-09 Eddie Hungopt_expr -fine to trim LSBs of $alu too
2019-08-09 Eddie HungAdd alumacc versions of opt_expr tests
2019-08-09 Eddie HungAdd new $alu test, remove wreduce
2019-08-09 Clifford WolfDisable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default...
2019-08-09 Eddie HungCleanup some more
2019-08-09 whitequarkMerge pull request #1267 from whitequark/proc_prune...
2019-08-09 Eddie HungSimplify opt_expr tests using equiv_opt
2019-08-09 Eddie HungA bit more on where $lcu comes from
2019-08-09 Eddie HungAdd more comments
2019-08-09 Eddie HungAdd __STDC_FORMAT_MACROS before <inttypes.h> as per...
2019-08-09 Miodrag MilanovicABC requires it like this
2019-08-09 Miodrag MilanovicPropagate parameters for Travis build
2019-08-08 Eddie HungRemove muxY and ffY for now
2019-08-08 Eddie HungRemove signed from ports in +/xilinx/dsp_map.v
2019-08-08 Eddie HungRework ice40_dsp to map to SB_MAC16 earlier, and check...
2019-08-08 Eddie HungCombine techmap calls
2019-08-08 Eddie HungOnly pack registers if {A,B,P}REG = 0, do not pack...
2019-08-08 Eddie HungMove xilinx_dsp to before alumacc
2019-08-08 Eddie HungDisable $dffe
2019-08-08 Eddie HungINMODE is 5 bits
2019-08-08 Eddie HungFix copy-pasta typo
2019-08-08 Eddie HungAdd a few comments to document $alu and $lcu
2019-08-08 Eddie HungMerge pull request #1264 from YosysHQ/eddie/fix_1254
2019-08-08 Eddie HungMerge pull request #1266 from YosysHQ/eddie/ice40_full_...
2019-08-08 David Shahecp5: Replace '-dsp' with inverse logic '-nodsp' to...
2019-08-08 David Shahecp5: Bring up to date with mul2dsp changes
2019-08-08 David ShahMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
2019-08-08 David ShahDSP48E1 sim model: add SIMD tests
2019-08-08 David ShahDSP48E1 model: test CE inputs
2019-08-08 David ShahDSP48E1 sim model: fix seq tests and add preadder tests
2019-08-08 David ShahDSP48E1 sim model: seq test working
2019-08-08 David ShahDSP48E1 sim model: Comb, no pre-adder, mode working
2019-08-08 David Shah[wip] sim model testing
2019-08-08 David Shah[wip] sim model testing
2019-08-08 whitequarkproc_prune: fix handling of exactly identical assigns.
2019-08-08 Eddie HungRemove dump call
2019-08-08 Eddie HungMove tests/various/opt* into tests/opt/
2019-08-08 Eddie HungRemove ice40_unlut call, simply do equiv_opt on synth_ice40
2019-08-08 Eddie HungAdd testcase from removed opt_ff.{v,ys}
2019-08-07 Eddie HungRemove tests/opt/opt_ff.{v,ys} as they don't seem to...
2019-08-07 Eddie HungAllow whitebox modules to be overwritten
2019-08-07 Eddie HungUpdate CHANGELOG
2019-08-07 Eddie HungAdd ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER...
2019-08-07 Eddie HungAdd test
2019-08-07 Eddie HungRemove ice40_unlut
2019-08-07 Eddie HungWrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER
2019-08-07 Eddie HungFix compile error
2019-08-07 Eddie HungRun "opt_expr -fine" instead of "wreduce" due to #1213
2019-08-07 Eddie HungDo not SigSpec::extract() beyond bounds
2019-08-07 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-07 Eddie Hungopt_lut to ignore LUT cells, or those that drive bits...
2019-08-07 Eddie HungDo not pack registers if (* keep *)
2019-08-07 Eddie HungMerge pull request #1248 from YosysHQ/eddie/abc9_speedup
2019-08-07 Eddie Hungsubstr() -> compare()
2019-08-07 Eddie HungRTLIL::S{0,1} -> State::S{0,1} for headers
2019-08-07 Eddie HungRTLIL::S{0,1} -> State::S{0,1}
2019-08-07 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-07 Eddie HungRemove std:: namespace
2019-08-07 Eddie Hung'make clean' to not remove anything abc
2019-08-07 Eddie Hungstoi -> atoi
2019-08-07 1138-4EBdockerfile: use 'python:3-slim-buster' base image
2019-08-07 1138-4EBdockerfile: use PREFIX instead of cp
2019-08-07 Jim LawsonMerge branch 'master' into firrtl_err_on_unsupported_cell
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