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yosys.git
2016-03-19
Sergey Kvachonok
Support calling out to an external ABC.
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2016-03-19
Clifford Wolf
Added $display %m support, fixed mem leak in $display...
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2016-03-19
Clifford Wolf
Added black box modules for all the 7-series design...
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2016-03-18
Clifford Wolf
Fixed localparam signdness, fixes #127
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2016-03-18
Clifford Wolf
Set "nosync" attribute on internal task/function wires
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2016-03-15
Clifford Wolf
Fixed Verilog parser fix and more similar improvements
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2016-03-15
Andrew Becker
Use left-recursive rule for cell_port_list in Verilog...
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2016-03-14
Clifford Wolf
Bugfix in write_verilog for RTLIL processes
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2016-03-11
Clifford Wolf
Cleanups and improvements in examples/cmos/
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2016-03-11
Clifford Wolf
Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
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2016-03-10
Clifford Wolf
Fixed typos in verilog_defaults help message
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2016-03-08
Clifford Wolf
Added "write_edif -nogndvcc"
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2016-03-08
Clifford Wolf
Added examples/cxx-api/evaldemo.cc
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2016-03-07
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-03-07
Clifford Wolf
Using "mfs" and "lutpack" in ABC lut mapping
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2016-03-05
Uros Platise
Completed ngspice digital example with verilog tb
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2016-03-02
Clifford Wolf
Added digital (xspice) example code to examples/cmos/
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2016-03-02
Clifford Wolf
Be more conservative with net names in spice output
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2016-02-29
Clifford Wolf
Merge pull request #119 from SebKuzminsky/spelling...
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2016-02-28
Sebastian Kuzminsky
user-facing spelling fixes
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2016-02-26
Clifford Wolf
We are now in 0.6+ development
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2016-02-26
Clifford Wolf
Yosys 0.6
yosys-0.6
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2016-02-24
Clifford Wolf
Fixed BLIF parser for empty port assignments
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2016-02-15
Clifford Wolf
Use easyer-to-read unoptimized ceil_log2()
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2016-02-15
Clifford Wolf
Updated ABC to ae7d65e71adc
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2016-02-14
Clifford Wolf
Updated command reference in manual
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2016-02-14
Clifford Wolf
Changelog for upcoming 0.6 release
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2016-02-14
Clifford Wolf
Fixed more visual studio warnings
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2016-02-13
Clifford Wolf
Fixed some visual studio warnings
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2016-02-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-02-13
Clifford Wolf
Added "int ceil_log2(int)" function
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2016-02-13
Clifford Wolf
Fixed MXE ABC build
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2016-02-13
Clifford Wolf
Run dffsr2dff in synth_xilinx
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2016-02-13
Clifford Wolf
Support for more Verific primitives (patch I got per...
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2016-02-08
Clifford Wolf
Updated ABC
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2016-02-07
Clifford Wolf
Work around DDR dout sim glitches in ice40 SB_IO sim...
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2016-02-07
Clifford Wolf
Updated ABC
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2016-02-04
Clifford Wolf
Added "stat -liberty" for calculating chip area
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2016-02-03
Clifford Wolf
Bugfix in Verific front-end
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2016-02-02
Clifford Wolf
Updated verific build instructions
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2016-02-02
Clifford Wolf
Improved dffsr2dff pass
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2016-02-02
Clifford Wolf
Added dffsr2dff
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2016-02-02
Clifford Wolf
Added addBufGate module method
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2016-02-02
Clifford Wolf
Use alphanumerical order instead of idstring idx in...
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2016-02-01
Clifford Wolf
Added CodeOfConduct
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2016-02-01
Clifford Wolf
Updated ABC to hg rev ee212a9e94df
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2016-02-01
Clifford Wolf
Progress in cell library documentation
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2016-02-01
Clifford Wolf
Added "abc -luts" option, Improved Xilinx logic mapping
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2016-02-01
Clifford Wolf
Improvements in dfflibmap (FFs with Q/QN outputs, DFFs...
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2016-02-01
Clifford Wolf
SigMap performance improvement
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2016-02-01
Clifford Wolf
hashlib mfp<> performance improvements
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2016-01-31
Clifford Wolf
Added reserve() method to haslib classes and
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2016-01-31
Clifford Wolf
Merge branch 'rtlil_remove2_speedup' of https://github...
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2016-01-31
Clifford Wolf
More clang sanitizer stuff
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2016-01-31
Rick Altherr
rtlil: Improve performance of SigSpec::extract(SigSpec...
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2016-01-31
Rick Altherr
rtlil: speed up SigSpec::sort_and_unify()
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2016-01-31
Rick Altherr
rtlil: improve performance of SigSpec::replace(SigSpec...
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2016-01-31
Rick Altherr
genrtlil: avoid converting SigSpec to set<SigBit> when...
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2016-01-31
Rick Altherr
rtlil: improve performance of SigSpec::remove2(SigSpec...
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2016-01-31
Clifford Wolf
Meaningless coding style change
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2016-01-31
Clifford Wolf
Merge branch 'rtlil_remove2_speedup' of https://github...
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2016-01-31
Clifford Wolf
Addedd clang sanitizers
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2016-01-30
Rick Altherr
rtlil: rewrite remove2() to avoid copying
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2016-01-30
Rick Altherr
rtlil: duplicate remove2() for std::set<>
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2016-01-30
Rick Altherr
rtlil: change IdString comparison operators to take...
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2016-01-08
Clifford Wolf
Added "equiv_struct -fwonly"
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2016-01-08
Clifford Wolf
Bugfixes in equiv_struct
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2016-01-08
Clifford Wolf
Added "submod -copy"
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2016-01-06
Clifford Wolf
Added "write_blif -cname" mode
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2016-01-06
Clifford Wolf
Added "equiv_struct -maxiter <N>"
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2016-01-06
Clifford Wolf
Added "equiv_add -try" mode
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2015-12-22
Clifford Wolf
Fixed "splitnets -ports" for hierarchical designs
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2015-12-22
Clifford Wolf
Re-run ice40_opt in "synth_ice40 -abc2"
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2015-12-22
Clifford Wolf
Improvements in ice40_opt
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2015-12-22
Clifford Wolf
Bugfix in ice40_ffinit
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2015-12-22
Clifford Wolf
Improved ice40_ffinit
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2015-12-22
Clifford Wolf
Run opt_const before check in default scripts
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2015-12-20
Clifford Wolf
Added %R select expression
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2015-12-20
Clifford Wolf
Various improvements in BLIF front-end
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2015-12-20
Clifford Wolf
Added yosys-smtbmc -S
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2015-12-15
Clifford Wolf
Merge pull request #110 from scanlime/master
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2015-12-15
Micah Elizabeth...
Mac build fix, gsed -> sed
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2015-12-15
Micah Elizabeth...
Remove nonportable "-r" option from xargs
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2015-12-08
Clifford Wolf
Added "synth_ice40 -abc2"
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-12-06
Cotton Seed
Added LO to ICESTORM_LC for LUT cascade route.
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2015-12-02
Clifford Wolf
Improved proc_mux performance for huge always blocks
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2015-12-02
Clifford Wolf
Added default values for hashlib at() methods
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2015-11-30
Clifford Wolf
Re-added SigMap::allbits()
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2015-11-30
Clifford Wolf
Added tests/simple/graphtest.v
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2015-11-29
Clifford Wolf
Fixed oom bug in ilang parser
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2015-11-27
Clifford Wolf
Fixed performance bug in ilang parser
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2015-11-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-11-26
Clifford Wolf
Removed dangling ';' in rtlil.h
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2015-11-26
Clifford Wolf
Added ice40_ffinit pass
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2015-11-24
Clifford Wolf
Added PRIM_DLATCHRS support to verific front-end
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2015-11-24
Clifford Wolf
Fixed WE/RE usage in iCE40 BRAM mapping
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2015-11-23
Clifford Wolf
Fixed handling of re-declarations of wires in tasks...
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2015-11-19
Clifford Wolf
Added torder command
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2015-11-16
Clifford Wolf
Fixed performance bug in Verific importer
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