git.libre-soc.org Git - yosys.git/shortlog

2014-03-13	Siesh1oo	- kernel/register.h, kernel/driver.cc: refactor rewrit...	commit \| commitdiff \| tree
2014-03-13	Siesh1oo	- Makefile: don't export DYLD_LIBRARY_PATH/LD_LIBRARY_...	commit \| commitdiff \| tree
2014-03-13	Siesh1oo	- .gitignore: ignore qmake/OSX package libs/svgviewer...	commit \| commitdiff \| tree
2014-03-13	Siesh1oo	- Makefile: include $(PWD) in PATH, since 'make test...	commit \| commitdiff \| tree
2014-03-13	Siesh1oo	- Makefile: fix typo in LDFLAGS: obviously -L, not...	commit \| commitdiff \| tree
2014-03-13	Siesh1oo	- Makefile: export PATH=${DESTDIR}/bin:$(PATH) and...	commit \| commitdiff \| tree
2014-03-13	Siesh1oo	- Makefile: resolve merge conflict.	commit \| commitdiff \| tree
2014-03-12	Clifford Wolf	Some fixes in libs/minisat (thanks to Siesh1oo)	commit \| commitdiff \| tree
2014-03-12	Siesh1oo	- kernel/register.h, kernel/driver.cc: refactor rewrit...	commit \| commitdiff \| tree
2014-03-12	Clifford Wolf	Fixed dependencies of "make test"	commit \| commitdiff \| tree
2014-03-12	Clifford Wolf	Added libs/minisat (copy of minisat git master)	commit \| commitdiff \| tree
2014-03-11	Clifford Wolf	OSX compatible creation of stdcells.inc, using code...	commit \| commitdiff \| tree
2014-03-11	Clifford Wolf	Merged addition of SED makefile variable from github...	commit \| commitdiff \| tree
2014-03-11	Clifford Wolf	Merged a few fixes for non-posix systems from github...	commit \| commitdiff \| tree
2014-03-11	Clifford Wolf	Added support for `line compiler directive	commit \| commitdiff \| tree
2014-03-11	Clifford Wolf	Fixed memory corruption in passes/abc/blifparse.cc	commit \| commitdiff \| tree
2014-03-11	Clifford Wolf	Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh	commit \| commitdiff \| tree
2014-03-11	Clifford Wolf	Use "verilog -noattr" in tests/techmap/mem_simple_4x1...	commit \| commitdiff \| tree
2014-03-10	Clifford Wolf	Fixed a typo in RTLIL::Module::addReduce...	commit \| commitdiff \| tree
2014-03-10	Clifford Wolf	Improved verific command (added support for some operators)	commit \| commitdiff \| tree
2014-03-10	Clifford Wolf	Improvements in verific command	commit \| commitdiff \| tree
2014-03-10	Clifford Wolf	Added RTLIL::Module::add... helper methods	commit \| commitdiff \| tree
2014-03-09	Clifford Wolf	Added "verific" command	commit \| commitdiff \| tree
2014-03-09	Clifford Wolf	Fixed dumping of timing() { .. } block in libparse	commit \| commitdiff \| tree
2014-03-09	Clifford Wolf	Verbose reading of liberty and constr files in ABC...	commit \| commitdiff \| tree
2014-03-07	Clifford Wolf	Fixed bug in freduce command	commit \| commitdiff \| tree
2014-03-07	Clifford Wolf	Some minor code cleanups in freduce command	commit \| commitdiff \| tree
2014-03-07	Clifford Wolf	Bugfix in ilang frontend autoidx recovery	commit \| commitdiff \| tree
2014-03-07	Clifford Wolf	Use log_abort() and log_assert() in BTOR backend	commit \| commitdiff \| tree
2014-03-06	Clifford Wolf	Added freduce -dump	commit \| commitdiff \| tree
2014-03-06	Clifford Wolf	Added freduce -stop	commit \| commitdiff \| tree
2014-03-06	Clifford Wolf	Fixed gcc compiler warning	commit \| commitdiff \| tree
2014-03-06	Clifford Wolf	Fixed undef handling in opt_reduce	commit \| commitdiff \| tree
2014-03-06	Clifford Wolf	Fixes for improved techmap of shifts with large B inputs	commit \| commitdiff \| tree
2014-03-06	Clifford Wolf	Fixed use of frozen literals in SatGen	commit \| commitdiff \| tree
2014-03-06	Clifford Wolf	Strictly zero-extend unsigned A-inputs of shift operati...	commit \| commitdiff \| tree
2014-03-06	Clifford Wolf	Added techmap -max_iter option	commit \| commitdiff \| tree
2014-03-06	Clifford Wolf	Improved techmap of shift with wide B inputs	commit \| commitdiff \| tree
2014-03-06	Clifford Wolf	Strictly zero-extend unsigned A-inputs of shift operations	commit \| commitdiff \| tree
2014-03-05	Clifford Wolf	Switched to EZMINISAT_SIMPSOLVER as default SAT solver	commit \| commitdiff \| tree
2014-03-05	Clifford Wolf	Include id2ast pointers when dumping AST	commit \| commitdiff \| tree
2014-03-05	Clifford Wolf	Fixed merging of compatible wire decls in AST frontend	commit \| commitdiff \| tree
2014-03-05	Clifford Wolf	Bugfix in recursive AST simplification	commit \| commitdiff \| tree
2014-03-03	Clifford Wolf	fixed freduce for Minisat::SimpSolver: use frozen_literal()	commit \| commitdiff \| tree
2014-03-03	Clifford Wolf	ezSAT: Added frozen_literal() API	commit \| commitdiff \| tree
2014-03-03	Clifford Wolf	ezSAT: Fixed handling of eliminated Literals, added...	commit \| commitdiff \| tree
2014-03-01	Clifford Wolf	Added ezSAT::eliminated API to help the SAT solver...	commit \| commitdiff \| tree
2014-03-01	Clifford Wolf	ezSAT bugfix: don't call virtual methods in base class...	commit \| commitdiff \| tree
2014-03-01	Clifford Wolf	Removed ezSAT::assumed() API	commit \| commitdiff \| tree
2014-03-01	Clifford Wolf	Removed ezSAT built-in brute-froce solver	commit \| commitdiff \| tree
2014-03-01	Clifford Wolf	Fixed vhdl2verilog temp dir name	commit \| commitdiff \| tree
2014-03-01	Clifford Wolf	Fixed vhdl2verilog help message	commit \| commitdiff \| tree
2014-02-27	Clifford Wolf	Fixed const folding of $bu0 cells	commit \| commitdiff \| tree
2014-02-26	Clifford Wolf	Fixed bit-extending in $mux argument (use $bu0 instead...	commit \| commitdiff \| tree
2014-02-26	Clifford Wolf	Added support for $bu0 to SatGen	commit \| commitdiff \| tree
2014-02-24	Clifford Wolf	Don't blow up constants unneccessarily in Verilog frontend	commit \| commitdiff \| tree
2014-02-23	Clifford Wolf	Added support for Minisat::SimpSolver + ezSAT frezze...	commit \| commitdiff \| tree
2014-02-23	Clifford Wolf	Fixed small memory leak in Pass::call()	commit \| commitdiff \| tree
2014-02-22	Clifford Wolf	Fixed bug in generation of undefs for $memwr MUXes	commit \| commitdiff \| tree
2014-02-22	Clifford Wolf	Fixed bug (typo) in passes/opt/opt_const.cc	commit \| commitdiff \| tree
2014-02-22	Clifford Wolf	Added $lut support to blif backend (by user eddiehung...	commit \| commitdiff \| tree
2014-02-22	Clifford Wolf	Added ezMiniSat EZMINISAT_INCREMENTAL compile-time...	commit \| commitdiff \| tree
2014-02-22	Clifford Wolf	Made MiniSat solver backend configurable in ezminisat.h	commit \| commitdiff \| tree
2014-02-21	Clifford Wolf	Added workaround for vhdl-style edge triggers from...	commit \| commitdiff \| tree
2014-02-21	Clifford Wolf	Added vhdl2verilog	commit \| commitdiff \| tree
2014-02-21	Clifford Wolf	Progress in presentation	commit \| commitdiff \| tree
2014-02-21	Clifford Wolf	Better handling of nameDef and nameRef in edif backend	commit \| commitdiff \| tree
2014-02-21	Clifford Wolf	Fixed instantiating multi-bit ports in edif backend	commit \| commitdiff \| tree
2014-02-21	Clifford Wolf	Use private namespace in mem_simple_4x1_map	commit \| commitdiff \| tree
2014-02-21	Clifford Wolf	Added tests/techmap/mem_simple_4x1	commit \| commitdiff \| tree
2014-02-21	Clifford Wolf	Renamed "write_blif -subckt" to "write_blif -icells...	commit \| commitdiff \| tree
2014-02-21	Clifford Wolf	Progress in presentation	commit \| commitdiff \| tree
2014-02-20	Clifford Wolf	Progress in presentation	commit \| commitdiff \| tree
2014-02-20	Clifford Wolf	Added _TECHMAP_REPLACE_ feature to techmap	commit \| commitdiff \| tree
2014-02-20	Clifford Wolf	Added "extract -ignore_parameters" and "extract -ignore...	commit \| commitdiff \| tree
2014-02-20	Clifford Wolf	Added "extract -map %<design_name>"	commit \| commitdiff \| tree
2014-02-20	Clifford Wolf	Added "design -push" and "design -pop"	commit \| commitdiff \| tree
2014-02-20	Clifford Wolf	Progress in presentation	commit \| commitdiff \| tree
2014-02-20	Clifford Wolf	Added connwrappers command	commit \| commitdiff \| tree
2014-02-20	Clifford Wolf	Cleanups in handling of read_verilog -defer and -icells	commit \| commitdiff \| tree
2014-02-20	Clifford Wolf	Progress in presentation	commit \| commitdiff \| tree
2014-02-19	Clifford Wolf	Added vcd2txt.pl and txt2tikztiming.py (tests/tools...	commit \| commitdiff \| tree
2014-02-18	Clifford Wolf	Merge branch 'master' of github.com:cliffordwolf/yosys	commit \| commitdiff \| tree
2014-02-18	Clifford Wolf	Progress in presentation	commit \| commitdiff \| tree
2014-02-18	Clifford Wolf	Added techmap support for _TECHMAP_CONNMAP_*_	commit \| commitdiff \| tree
2014-02-18	Clifford Wolf	Added "sat -dump_cnf"	commit \| commitdiff \| tree
2014-02-18	Clifford Wolf	Coding style corrections in SatHelper::dump_model_to_vcd()	commit \| commitdiff \| tree
2014-02-18	Clifford Wolf	Improved non-verbose ezSAT::printDIMACS() format	commit \| commitdiff \| tree
2014-02-18	Clifford Wolf	Added "sat -initsteps"	commit \| commitdiff \| tree
2014-02-17	Clifford Wolf	Added Verilog support for "`default_nettype none"	commit \| commitdiff \| tree
2014-02-17	Clifford Wolf	Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd"...	commit \| commitdiff \| tree
2014-02-17	Andrew Zonenberg	Added "-dump_fail_to_vcd" argument to SAT solver	commit \| commitdiff \| tree
2014-02-17	Clifford Wolf	Progress in presentation	commit \| commitdiff \| tree
2014-02-17	Clifford Wolf	Better preserve wires when flattening (in comparison...	commit \| commitdiff \| tree
2014-02-16	Clifford Wolf	Progress in presentation	commit \| commitdiff \| tree
2014-02-16	Clifford Wolf	Added some additional checks to techmap	commit \| commitdiff \| tree
2014-02-16	Clifford Wolf	Added CONSTMSK and CONSTVAL feature to techmap	commit \| commitdiff \| tree
2014-02-16	Clifford Wolf	Fixed handling of "keep" attribute on wires in opt_clean	commit \| commitdiff \| tree
2014-02-16	Clifford Wolf	Added a warning note about error reporting to read_veri...	commit \| commitdiff \| tree
2014-02-16	Clifford Wolf	Progress in presentation	commit \| commitdiff \| tree
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