nmigen.git
2020-05-24 Robin Ole Heinemannhdl.ast: fix typo
2020-05-22 whitequarkback.verilog: fall back to nmigen_yosys package.
2020-05-21 whitequarkUpdate .gitignore.
2020-05-21 whitequarkvendor.intel: don't use `write_verilog -decimal`.
2020-05-21 whitequarkvendor.intel: double-quote Tcl values rather than brace...
2020-05-21 whitequarkvendor.xilinx_{7series,ultrascale}: don't use `write_ve...
2020-05-20 whitequarkbuild.plat: skip clock constraints on unused signals.
2020-05-20 whitequarkvendor.xilinx_{7series,ultrascale}: add (*keep*) on...
2020-05-20 whitequarkhdl.ast: add const-shift operations.
2020-05-19 whitequarkhdl.ast: clarify docs for Value.rotate_{left,right}.
2020-05-19 whitequarkhdl.dsl: check for unique domain name.
2020-05-19 whitequarkback.rtlil: handle signed and large Instance parameters...
2020-05-17 whitequarktracer: fix get_var_name() to work on toplevel attributes.
2020-05-08 Gwenhael Goavec... vendor.lattice_machxo2: generate binary bitstreams.
2020-05-02 whitequarkplat, vendor: systematically escape net and file names...
2020-04-28 whitequarkback.rtlil: fix incorrect escaping of signed parameters.
2020-04-27 whitequarkhdl.ast: use SignalSet, not ValueSet, for _[lr]hs_signa...
2020-04-27 whitequarklib.cdc: add missing documentation for AsyncFFSynchroni...
2020-04-24 awyglelib.fifo: add r_rst output for AsyncFIFO{,Buffered}.
2020-04-24 awyglehdl.ir: typecheck `convert(ports=)` more carefully.
2020-04-24 whitequarkREADME: link directly to Yosys build instructions.
2020-04-23 Teguh Hofsteeback.verilog: add workaround for evaluation Verific...
2020-04-22 Teguh Hofsteeback.verilog: make Yosys version check compatible with...
2020-04-21 Kate Temkinvendor: use nextpnr -12k for -12F devices; remove theor...
2020-04-16 anuejnhdl.rec: make Record inherit from UserValue. working_23jun2020
2020-04-15 whitequarkback.rtlil: translate enum decoders to Yosys enum attri...
2020-04-14 whitequarkbuil.plat: enable strict undefined behavior in Jinja2.
2020-04-13 whitequarkback.rtlil: don't emit connections to zero width ports.
2020-04-13 whitequarkback.rtlil: refuse to create extremely large wires.
2020-04-13 whitequarkback.rtlil: fix expansion of Part() for partial dummy...
2020-04-13 whitequarkback.rtlil: fix legalization of Part() with stride.
2020-04-13 whitequarkClarify a few comments. NFC.
2020-04-13 Dan Ravenslofthdl.ast: add Value.{rotate_left,rotate_right}.
2020-04-13 whitequarkTravis: require tests to pass on pypy3.
2020-04-13 whitequarkTravis: upgrade to bionic.
2020-04-12 whitequarkbuild.run: fix BuildProducts.extract to work with subdi...
2020-04-12 whitequarkhdl.rec: improve repr() for Layout.
2020-04-12 whitequarkhdl.ast: improve repr() for Shape.
2020-04-12 whitequarkbuild.plat: don't check for toolchain presence if do_bu...
2020-04-08 Stuart Olsenback.pysim: Clear pending updates after they are effected
2020-04-07 Stuart Olsenback.pysim: Eliminate duplicate dict lookup in VCD...
2020-04-07 Stuart Olsenback.pysim: Reuse clock simulation commands
2020-04-05 whitequarkhdl.mem: fix source location of ReadPort.en.
2020-04-03 whitequarkback.pysim: fix emission of undriven traces to VCD...
2020-04-02 whitequarksetup: bump pyvcd to ~=0.2.
2020-04-02 Jacob LifshayAdd support for using non-compat Elaboratable instances...
2020-04-02 whitequarksetup: tighten version constraint on Jinja2.
2020-03-22 whitequarkhdl.ast: implement abs() on values.
2020-03-20 WRansohoffvendor.lattice_ice40: add support for SB_[LH]FOSC as...
2020-03-15 Nicolas Robinvendor: fix typo `async_ff_sync`
2020-03-15 Stuart Olsenback.pysim: implement modulus operator.
2020-03-14 awygleCorrectly handle resets in AsyncFIFO.
2020-03-12 whitequarkvendor: fix a few issues in commit 2f8669ca.
2020-03-08 awyglelib.cdc: extract AsyncFFSynchronizer.
2020-02-19 whitequarkhdl.ast: fix off-by-1 in Initial.__init__().
2020-02-19 whitequarkback.pysim: fix RHS codegen for Cat() and Repl(......
2020-02-19 whitequarkback.pysim: optionally allow introspecting generated...
2020-02-16 awyglenmigen.compat.genlib.cdc: add PulseSynchronizer.
2020-02-16 awyglenmigen.lib.cdc: port PulseSynchronizer.
2020-02-14 whitequarkTravis: prune dependencies. v0.2
2020-02-14 whitequarkTravis: test on Python 3.8.
2020-02-12 whitequarkcli: update use of deprecated code.
2020-02-12 whitequarkback.pysim: accept write_vcd(vcd_file=None).
2020-02-09 whitequarksetup: update project URLs.
2020-02-09 whitequarkdoc: remove outdated files and references to them.
2020-02-08 whitequarkREADME: link to IRC channel.
2020-02-08 whitequarkREADME: consolidate requirements in the Installation...
2020-02-07 whitequarktest_build_res: fix after commit 3e2ecdf2.
2020-02-06 whitequarkbuild.res,vendor: place clock constraint on port, not...
2020-02-06 whitequarkxilinx_{7series,ultrascale}: run `report_methodology`.
2020-02-06 whitequarkhdl.ast: add Value.{as_signed,as_unsigned}.
2020-02-06 whitequarktest_lib_fifo: define all referenced FSM states.
2020-02-06 whitequarkhdl.dsl: make referencing undefined FSM states an error.
2020-02-06 whitequarkhdl.ir: type check ports.
2020-02-06 whitequarkback.pysim: emit toplevel inputs in VCD files as well.
2020-02-06 whitequarkback.pysim: make `write_vcd(traces=)` actually use...
2020-02-06 whitequarkhdl.dsl: reject name mismatch in `m.domains.<name>...
2020-02-06 whitequarkhdl.dsl: type check when adding to m.domains.
2020-02-06 whitequarkhdl.mem: add synthesis attribute support.
2020-02-06 whitequarkhdl.mem: document Memory.
2020-02-04 whitequarkhdl.{ast,dsl}: allow whitespace in bit patterns.
2020-02-01 whitequarkhdl.ast: update documentation for Signal.
2020-02-01 whitequarkhdl.ast: prohibit shifts by signed value.
2020-02-01 whitequarkbuild.plat: align pipeline with Fragment.prepare().
2020-02-01 whitequarkhdl.dsl: don't allow inheriting from Module.
2020-02-01 whitequarkhdl.ast: warn on unused property statements (Assert...
2020-02-01 whitequark_unused: extract must-use logic from hdl.ir.
2020-01-31 whitequarkhdl.dsl: add missing case width check for Enum values.
2020-01-31 whitequarkREADME: clarify relationship to Migen.
2020-01-31 whitequarkhdl.dsl: make `if m.{If,Elif,Else}(...)` a syntax error.
2020-01-31 whitequarkback.rtlil: don't emit wires for empty signals.
2020-01-31 Mike Waltersvendor.lattice_ecp5: support internal oscillator (OSCG).
2020-01-31 Jaro Habigerbuild.dsl: allow strings to be used as connector numbers.
2020-01-31 Sylvain Munautvendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files...
2020-01-27 whitequarkUpdate README.
2020-01-18 whitequarkhdl.ir: resolve hierarchy conflicts before creating...
2020-01-17 whitequarkhdl.xfrm: transform drivers as well in DomainRenamer.
2020-01-12 whitequarkRemove everything deprecated in nmigen 0.1.
2020-01-11 Staf VerhaegenSignal: allow to use integral Enum for reset value.
2020-01-09 schwigivendor.intel: fix output enable width for XDR=0 case.
next