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yosys.git
2017-07-22
Clifford Wolf
Improve docs for verific bindings, add simply sby example
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2017-07-21
Clifford Wolf
Fix handling of empty cell port assignments (i.e. ignor...
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2017-07-21
Clifford Wolf
Fix "read_blif -wideports" handling of cells with wide...
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2017-07-21
Clifford Wolf
Add a paragraph about pre-defined macros to read_verilo...
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2017-07-21
Clifford Wolf
Add verilator support to testbenches generated by yosys...
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2017-07-18
Clifford Wolf
Change intptr_t to uintptr_t in hashlib.h
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2017-07-18
Clifford Wolf
Merge pull request #363 from rqou/master
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2017-07-17
Robert Ou
makefile: Add the option to use libtermcap
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2017-07-17
Robert Ou
Fix build warnings for win64
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2017-07-14
Clifford Wolf
Add $alu to list of supported cells for "stat -width"
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2017-07-12
Clifford Wolf
Generate FSM-style testbenches in smtbmc
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2017-07-11
Clifford Wolf
Fix the fixed handling of x-bits in EDIF back-end
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2017-07-11
Clifford Wolf
Fix handling of x-bits in EDIF back-end
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2017-07-10
Clifford Wolf
Add attributes and parameter support to JSON front-end
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2017-07-10
Clifford Wolf
Add techlibs/xilinx/lut2lut.v
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2017-07-08
Clifford Wolf
Add JSON front-end
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2017-07-07
Clifford Wolf
Change s/asserts/assertions/ in yosys-smtbmc log messages
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2017-07-07
Clifford Wolf
Add "yosys-smtbmc --presat"
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2017-07-05
Clifford Wolf
Fix generation of multiple outputs for same AIG node...
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2017-07-05
Clifford Wolf
Add write_table command
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2017-07-04
Clifford Wolf
Add Verific Release information to log
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2017-07-03
Clifford Wolf
Fix some c++ clang compiler errors
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2017-07-03
Clifford Wolf
Apply minor coding style changes to coolrunner2 target
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2017-07-03
Clifford Wolf
Merge pull request #352 from rqou/master
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2017-07-03
Clifford Wolf
Merge pull request #356 from set-soft/clean-test
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2017-07-03
Clifford Wolf
Merge pull request #355 from set-soft/exclude_TBUF_merge
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2017-07-03
Salvador E...
Added the test outputs to the clean target
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2017-07-03
Salvador E...
Excluded $_TBUF_ from opt_merge pass
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2017-07-03
Clifford Wolf
Remove unneeded delays in smtbmc vlogtb
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2017-07-03
Clifford Wolf
Include output ports with constant driver in AIGER...
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2017-07-01
Clifford Wolf
Add "yosys-smtbmc --vlogtb-top"
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2017-07-01
Clifford Wolf
Fix and_or_buffer optimization in opt_expr for signed...
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2017-07-01
Clifford Wolf
Fix smtbmc vlogtb bug in $anyseq handling
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2017-06-30
Clifford Wolf
Add "design -import"
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2017-06-30
Clifford Wolf
Add chtype command
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2017-06-30
Clifford Wolf
Add $tribuf to opt_merge blacklist
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2017-06-27
Clifford Wolf
Merge pull request #353 from azonenberg/master
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2017-06-26
Robert Ou
coolrunner2: Add a few more primitives
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2017-06-26
Robert Ou
coolrunner2: Initial mapping of latches
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2017-06-26
Robert Ou
coolrunner2: Initial mapping of DFFs
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2017-06-26
Robert Ou
coolrunner2: Remove redundant INVERT_PTC
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2017-06-26
Robert Ou
coolrunner2: Remove debug prints
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2017-06-26
Robert Ou
coolrunner2: Correctly handle $_NOT_ after $sop
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2017-06-26
Robert Ou
coolrunner2: Also construct the XOR cell in the macrocell
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2017-06-26
Robert Ou
coolrunner2: Initial techmapping for $sop
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2017-06-24
Andrew Zonenberg
greenpak4_counters: Changed generation of primitive...
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2017-06-24
Robert Ou
coolrunner2: Initial commit
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2017-06-20
Clifford Wolf
Fix handling of init values in "abc -dff" and "abc...
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2017-06-20
Clifford Wolf
Fix history namespace collision
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2017-06-20
Clifford Wolf
Store command history when terminating with an error
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2017-06-20
Clifford Wolf
Switched abc "clock domain not found" error to log_cmd_...
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2017-06-07
Clifford Wolf
Fix generation of vlogtb output in yosys-smtbmc for...
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2017-06-01
Clifford Wolf
Fix handling of Verilog ~& and ~| operators
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2017-05-31
Clifford Wolf
Update ABC to hg rev efbf7f13ea9e
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2017-05-31
Clifford Wolf
Add dff2ff.v techmap file
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2017-05-30
Clifford Wolf
Fix AIGER back-end for multiple symbols per input/latch...
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2017-05-28
Clifford Wolf
Add "setundef -anyseq"
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2017-05-28
Clifford Wolf
Improve write_aiger handling of unconnected nets and...
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2017-05-27
Clifford Wolf
Change default smt2 solver to yices (Yices 2 has switch...
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2017-05-24
Clifford Wolf
Add aliases for common sets of gate types to "abc -g"
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2017-05-23
Clifford Wolf
Add examples/osu035
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2017-05-23
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-05-23
Clifford Wolf
Merge pull request #346 from azonenberg/master
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2017-05-23
Andrew Zonenberg
greenpak4_counters: Added support for parallel output...
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2017-05-17
Clifford Wolf
Add workaround for CBMC bug to SimpleC back-end
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2017-05-17
Clifford Wolf
Enable readline and tcl in mxe builds
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2017-05-17
Clifford Wolf
Add missing AndnotGate() and OrnotGate() declarations...
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2017-05-17
Clifford Wolf
Add $_ANDNOT_ and $_ORNOT_ gates
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2017-05-16
Clifford Wolf
Add <modname>_init() function generator to simpleC...
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2017-05-16
Clifford Wolf
Improve simplec back-end
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2017-05-15
Clifford Wolf
Improve simplec back-end
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2017-05-14
Clifford Wolf
Improve simplec back-end
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2017-05-13
Clifford Wolf
Improve simplec back-end
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2017-05-12
Clifford Wolf
Improve simplec back-end
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2017-05-12
Clifford Wolf
Added support for more gate types to simplec back-end
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2017-05-12
Clifford Wolf
Add first draft of simple C back-end
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2017-05-11
Clifford Wolf
Update ABC to hg rev e79576e10d72
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2017-05-08
Clifford Wolf
Fix boolector support in yosys-smtbmc
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2017-04-30
Clifford Wolf
Add support for localparam in module header
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2017-04-28
Clifford Wolf
Fix equiv_simple, old behavior now available with ...
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2017-04-26
Clifford Wolf
Add support for `resetall compiler directive
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2017-04-12
Clifford Wolf
Replace CRLF line endings with LF in de2i.qsf (quartus...
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2017-04-12
Larry Doolittle
Squelch trailing whitespace
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2017-04-07
Clifford Wolf
Add MAX10 and Cyclone IV items to CHANGELOG
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2017-04-07
Clifford Wolf
Merge pull request #337 from dh73/master
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2017-04-06
dh73
Add initial support for both MAX10 and Cyclone IV ...
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2017-04-05
Clifford Wolf
Add ConstEval defaultval feature
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2017-04-05
Clifford Wolf
Fix gcc compiler warning
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2017-03-28
Clifford Wolf
Add front-end detection for *.tcl files
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2017-03-27
Clifford Wolf
Add minisat 00_PATCH_typofixes.patch
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2017-03-27
Clifford Wolf
Remove use of <fpu_control.h> in minisat
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2017-03-20
Clifford Wolf
Add "write_smt2 -stdt" mode
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2017-03-19
Clifford Wolf
Add generation of logic cells to EDIF back-end runtest.py
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2017-03-19
Clifford Wolf
Fix EDIF: portRef member 0 is always the MSB bit
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2017-03-18
Clifford Wolf
Add simple EDIF test case generator and checker
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2017-03-14
Clifford Wolf
Fix verilog pre-processor for multi-level relative...
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2017-03-04
Clifford Wolf
Improve smt2 encodings of assert/assume/cover, better...
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2017-03-02
Clifford Wolf
Add write_aiger $anyseq support
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2017-03-01
Clifford Wolf
Allow $anyconst, etc. in non-formal SV mode
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2017-02-28
Clifford Wolf
Disable opt_merge for $anyseq and $anyconst
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