nmigen.git
2019-02-14 whitequarkhdl.ir: raise a more descriptive error on non-elaborata...
2019-01-26 whitequarkback.rtlil: accept ast.Const as cell parameter.
2019-01-26 whitequarkhdl.ast: fix ValueKey for Cat.
2019-01-26 whitequarkcompat.fhdl.module: fix typo.
2019-01-26 whitequarkcompat.fhdl.specials: fix __all__ list.
2019-01-26 whitequarkcompat.genlib.resetsync: add shim for AsyncResetSynchro...
2019-01-26 whitequarkcompat.fifo: fix _FIFOInterface deprecation wrapper.
2019-01-26 whitequarklib.cdc: add ResetSynchronizer.
2019-01-26 whitequarkback.pysim: support async reset.
2019-01-26 whitequarkback.pysim: give better names to unnamed fragments...
2019-01-26 whitequarkexamples: update for newer API.
2019-01-26 whitequarkback.rtlil: accept any elaboratable, not just fragments.
2019-01-26 whitequarkcompat: suppress deprecation warnings that are internal...
2019-01-26 whitequarktest.compat: reenable tests converting to Verilog.
2019-01-26 whitequarkcompat.sim: fix deprecated stdlib import.
2019-01-26 whitequarkhdl.ir: rename .get_fragment() to .elaborate().
2019-01-26 whitequarktest.compat: import tests from Migen as appropriate.
2019-01-26 whitequarkhdl.ast: fix shape calculation for *.
2019-01-25 whitequarkback.pysim: fix behavior of initial cycle for sync...
2019-01-22 whitequarklib.fifo: in FIFOInterface.read(), check readable on...
2019-01-22 whitequarkcompat.genlib.fifo: adjust _FIFOInterface shim to not...
2019-01-22 whitequarklib.fifo: fix typo in AsyncFIFO documentation.
2019-01-21 whitequarklib.fifo: add AsyncFIFO and AsyncFIFOBuffered.
2019-01-21 whitequarkback.pysim: wake up processes before ever committing...
2019-01-20 whitequarkcompat.genlib.cdc: add missing import.
2019-01-20 whitequarkcompat.genlib.cdc: add GrayCounter and GrayDecoder...
2019-01-20 whitequarklib.coding: add GrayEncoder and GrayDecoder.
2019-01-20 whitequarklib.coding: add width as attribute to all coders.
2019-01-19 whitequarklib.fifo: use memory in the FIFO model.
2019-01-19 whitequarklib.fifo: use model equivalence to simplify formal...
2019-01-19 whitequarkhdl.ast: implement shape for modulo operator.
2019-01-19 whitequarkhdl.ast: add Value.implies.
2019-01-19 whitequarkhdl.xfrm: mark internal registers used in lowering...
2019-01-19 whitequarkdoc: update COMPAT_SUMMARY.
2019-01-19 whitequarkfhdl.specials: add compatibility shim for Tristate.
2019-01-19 whitequarklib.fifo: fix simulation read/write methods to take...
2019-01-19 whitequarkcompat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOB...
2019-01-19 whitequarklib.fifo: formally verify FIFO contract.
2019-01-19 whitequarkhdl.ast: give Assert and Assume their own src_loc.
2019-01-18 whitequarkback.rtlil: only emit each AnyConst/AnySeq cell once.
2019-01-17 Alain Péteutcli: add missing default for `generate`
2019-01-17 whitequarklib.fifo: add basic formal specification.
2019-01-17 whitequarkhdl.ast: allow sampling ClockSignal, ResetSignal.
2019-01-17 whitequarkhdl.ast: add Past, Stable, Rose, Fell.
2019-01-17 whitequarkformal: extract from toplevel module.
2019-01-17 whitequarkhdl.xfrm: add SampleLowerer.
2019-01-17 whitequarkhdl.ast: add Sample.
2019-01-16 whitequarklib.fifo: port sync FIFO queues from Migen.
2019-01-16 whitequarkhdl.ast: fix naming of Signal.like() signals when trace...
2019-01-16 whitequarkback.rtlil: slightly nicer naming for $next signals...
2019-01-16 whitequarkback.rtlil: rename \sig$next to $next$sig.
2019-01-16 whitequarkTravis: install SymbiYosys and Yices2.
2019-01-15 whitequarkUnbreak 655d02d5.
2019-01-15 William D.... back.rtlil: Generate $anyconst and $anyseq cells.
2019-01-15 William D.... hdl.xfrm: Add on_AnyConst and on_AnySeq abstract method...
2019-01-15 William D.... hdl.ast: Add AnyConst and AnySeq value types.
2019-01-15 Sebastien BourdeauducqREADME: add LambdaConcept sponsorship
2019-01-14 whitequarklib.io: pass pin to platform.get_tristate().
2019-01-14 whitequarkhdl.ir: allow explicitly requesting flattening.
2019-01-14 whitequarklib.io: lower to platform-independent tristate buffer.
2019-01-14 whitequarkhdl: make ClockSignal and ResetSignal usable on LHS.
2019-01-13 whitequarkhdl.dsl: cases wider than switch test value are unreach...
2019-01-13 whitequarkhdl.dsl: accept (but warn on) cases wider than switch...
2019-01-13 whitequarkback.pysim: handle non-driven, non-port signals.
2019-01-13 whitequarkback.verilog: better error message if Yosys is not...
2019-01-08 whitequarkback.verilog: remove undriven check.
2019-01-06 Adam GreigGive the top level scope a name to fix VCD hierarchy.
2019-01-02 whitequarkhdl.ast: allow slicing [n:n] into n-bit value.
2019-01-02 whitequarkback.rtlil: translate empty slices correctly.
2019-01-02 William D.... back.rtlil: Generate RTLIL for Assert/Assume statements.
2019-01-02 William D.... hdl.xfrm: Add Assert and Assume abstract methods for...
2019-01-02 William D.... hdl.dsl: Support Assert and Assume where an Assign...
2019-01-02 William D.... hdl.ast: Add Assert and Assign statements.
2019-01-01 whitequarkhdl.ast: experimentally add Value._as_const.
2019-01-01 whitequarkback.rtlil: fix typo.
2019-01-01 whitequarkhdl.rec: include record name in error message.
2019-01-01 whitequarkhdl.rec: use a helpful error on unknown field reference.
2019-01-01 whitequarkhdl.mem: add DummyPort, for testing and verification.
2018-12-31 whitequarkback.rtlil: match shape of Array elements to ArrayProxy...
2018-12-31 whitequarkback.rtlil: fix typo.
2018-12-29 whitequarklib.cdc: fix tests to actually run.
2018-12-29 whitequarkback.pysim: warn if simulation is not run.
2018-12-28 whitequarkhdl.rec: add basic record support.
2018-12-28 whitequarktracer: factor out get_src_loc().
2018-12-27 whitequarklib.coding: fix tests to actually run, and fix code...
2018-12-27 whitequarkhdl.dsl: add support for fsm.ongoing().
2018-12-27 whitequarkhdl.mem: add missing __all__.
2018-12-26 Jean-François... compat.genlib.coding: fix import.
2018-12-26 whitequarklib.coding: port from Migen.
2018-12-26 whitequarklib.cdc: add tests for MultiReg.
2018-12-26 whitequarkhdl.dsl: forbid m.next= inside of FSM but outside of...
2018-12-26 whitequarkhdl.dsl: provide generated values for FSMs.
2018-12-26 whitequarkhdl.ir: add an API for retrieving generated values...
2018-12-26 whitequarkexamples: add an FSM usage example (UART receiver).
2018-12-26 whitequarkhdl.dsl: add signal decoder to FSM state signal.
2018-12-26 whitequarkhdl.dsl: implement FSM.
2018-12-26 whitequarkback.rtlil: clarify $verilog_initial_trigger behavior...
2018-12-24 whitequarkback.rtlil: unbreak d47c1f8a.
2018-12-24 whitequarkhdl.mem: allow omitting memory simulation logic.
2018-12-24 whitequarkback.rtlil: use one $meminit cell, not one per word.
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