libreriscv.git
2020-11-15 Luke Kenneth... add headings for modes
2020-11-15 Luke Kenneth... mention mode-switching idea (to 32-bit for 1 cycle)
2020-11-15 Luke Kenneth... add C-Bank switching instruction
2020-11-15 Luke Kenneth... try an addi
2020-11-15 Luke Kenneth... mention idea TODO of going into 32-bit mode for 1 instr...
2020-11-15 Luke Kenneth... clarify 16-bit encoding
2020-11-15 Luke Kenneth... add fmr. minor shuffle
2020-11-15 Luke Kenneth... add fmr. in 16-bit mode
2020-11-15 Luke Kenneth... add system, spr and unallocated C16
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2020-11-14 Luke Kenneth... add CR operations
2020-11-14 Luke Kenneth... move 16 bit compressed to separate page
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2020-11-14 Luke Kenneth... whitespace and update C tables
2020-11-14 Luke Kenneth... add OFSC 2020 talk
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2020-11-13 Cesar_StraussAdd Tomasulo model example
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2020-11-11 Tobias Platenadd dcbz and tlbio instruction needed by mmu
2020-11-10 Luke Kenneth... add minerva nmigen-soc example
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2020-11-05 Luke Kenneth... add EOMA68+LibreSOC gadie section
2020-11-05 Luke Kenneth... add EOMA68+LibreSOC gadie section
2020-11-05 Luke Kenneth... extend gaddie pitch
2020-11-05 Luke Kenneth... extend gaddie pitch
2020-11-05 Luke Kenneth... extend gaddie pitch
2020-11-05 Luke Kenneth... add gaddie pitch section for LibreSOC
2020-11-05 Luke Kenneth... update nlnet FAQ
2020-11-05 Luke Kenneth... update FAQ
2020-11-05 Luke Kenneth... add name tag to FAQ
2020-11-05 Luke Kenneth... add name tag to FAQ
2020-11-05 Luke Kenneth... add name tag to FAQ
2020-11-04 Luke Kenneth... add to nlnet FAQ
2020-11-04 colepoirier... (no commit message)
2020-11-04 Luke Kenneth... add to NLnet FAQ
2020-11-04 Luke Kenneth... add to NLnet FAQ
2020-11-04 Luke Kenneth... show tab on imag
2020-11-04 Luke Kenneth... update FPGA connector images
2020-11-04 Luke Kenneth... add circuit refs
2020-11-04 Luke Kenneth... change to use 3.3v on VERSA X3
2020-11-04 Luke Kenneth... add NLnet FAQ
2020-11-04 colepoirier... (no commit message)
2020-11-04 Cole PoirierHDL_wokflow update ulx3s jtag jumper wire connection...
2020-11-04 Cole PoirierHDL_workflow/ECP5_FPGA provide two images showing diffe...
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2020-11-04 Cole Poirierupdate photo for stlinkv2 JTAG wires in HDL_Workflow...
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2020-11-03 Luke Kenneth... colour-mark X3 VERSA ECP5 JTAG pins
2020-11-03 Luke Kenneth... update jtag table, add colour to images
2020-11-03 Luke Kenneth... add stlinkv2 photos
2020-11-03 Luke Kenneth... add stlinkv2 connector images
2020-11-03 Luke Kenneth... swap wires around to match ulx3s
2020-11-03 Luke Kenneth... format table
2020-11-03 Luke Kenneth... add ECP5 JTAG connections
2020-11-03 Luke Kenneth... add image links to ECP5 page
2020-11-03 Luke Kenneth... add versa ecp5 x3 photo
2020-11-03 Luke Kenneth... add VERSA-ECP5 images, rename FPGA page
2020-11-01 colepoirier... (no commit message)
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2020-11-01 Cole Poirieradd images to wiki for ulx3s jtag stlinkv2 wires
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2020-11-01 colepoirier... add page use ulx3s fpga gpio pins for Libre-SOC JTAG...
2020-10-31 Luke Kenneth... add cross-ref links
2020-10-31 Luke Kenneth... adjust image size
2020-10-31 Luke Kenneth... add description of table
2020-10-31 Luke Kenneth... change image size
2020-10-31 Luke Kenneth... add image size
2020-10-31 Luke Kenneth... add start of isa-to-virtual regs
2020-10-31 Luke Kenneth... add isa to virtual regs lookup
2020-10-30 Luke Kenneth... add clock switch resource
2020-10-30 Luke Kenneth... spelling
2020-10-30 Luke Kenneth... add 180nm tapeout to progress
2020-10-29 colepoirier... (no commit message)
2020-10-29 colepoirier... (no commit message)
2020-10-29 Luke Kenneth... whitespace
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