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litex.git
2012-01-27
Sebastien Bourdeauducq
Add on-chip SRAM
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2012-01-21
Sebastien Bourdeauducq
Use meaningful class names
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2012-01-20
Sebastien Bourdeauducq
Use new verilog.convert API
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2012-01-13
Sebastien Bourdeauducq
Wishbone: omit fixed LSBs
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2012-01-13
Sebastien Bourdeauducq
convtools -> tools
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2012-01-05
Sebastien Bourdeauducq
Convert -> convert
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2011-12-18
Sebastien Bourdeauducq
Use new syntax
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2011-12-17
Sebastien Bourdeauducq
uart: new design using FHDL and bank (TX only, incomplete)
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2011-12-17
Sebastien Bourdeauducq
32-device, 8-bit CSR bus
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2011-12-17
Sebastien Bourdeauducq
norflash tb: use get_fragment
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2011-12-17
Sebastien Bourdeauducq
Multiply system clock
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2011-12-17
Sebastien Bourdeauducq
clkfx module
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2011-12-16
Sebastien Bourdeauducq
Proper reset generation
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2011-12-16
Sebastien Bourdeauducq
Support the new FHDL syntax
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2011-12-16
Sebastien Bourdeauducq
Pay a bit more attention to PEP8
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2011-12-13
Sebastien Bourdeauducq
Initial import
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